PCI and PCI-X Compliance Test Library

The PCI and PCI-X Compliance Test Library which controls the Agilent Exerciser and Analyzer performs the tests briefly described below. In addition, there are over 50 PCI/PCI-X protocol tests which automatically run on the bus checking for various protocol errors (more information on the protocol tests can be obtained on the Agilent Web Site.

System Test

MLT

Master Latency Timer test. This test checks to see if Master Latency Register is set to Read only or Read/Write and that it is set to a correct value. If Read Only, it checks to see if set to a value of 16 or less. If Read/Write it verifies that it is zero after RST# and verifies that the high order bits are R/W.

PCIPOST

Analyzer software for PCIPOST test. This test is utilized to initialize the Base Address registers and to verify the address assignments.

PCIINT

Analyzer software will assert an interrupt on request from analyzer mailbox. OS dependent software will request an interrupt from the analyzer and verify the interrupt was received and processed correctly.

PCIDLOCK

OS dependent software will provide the analyzer card with the block of memory space to be used by the analyzer for the DLOCK test. The software will then execute reads and writes from/to the analyzer. Analyzer software will initiate writes and reads to the assigned memory space.

Add-in Card Test

CRDTST

CRDTST performs a number of tests including testing for correct values and operation for the Command Register, the Status register, and appropriate values for other configuration registers. The configuration register contents are displayed during CRDTST.

TYPE1

This test verifies correct configuration transaction decoding by the device.

PMTEST

This is a Power Management test which is utilized for testing several card Power Management capabilities, including correct use of the PM Capabilities register and the PM Control/Status register.

DISCARD

This test verifies card correctly repeats Retried PCI transactions.

Other Tests

More than 50 protocol tests are continuously run during bus operations monitoring for bus protocol errors. The signal sequence associated with the error is displayed and a file copied to diskette for later display.