| Time |
Title |
| 8:00 am - 9:00 am |
Registration in Foyer |
| 9:00 am - 10:00 am |
(1) PCIe 2.0 PHY Electrical Sub-Block - Part 1
(2) IOV Architecture Overview
(3) PCI-SIG Architecture Overview
(4) PCIe as Multiprocessor System Interconnect |
| 10:00 am - 11:00 am |
(1) PCIe 2.0 PHY Electrical Sub-Block - Part 2
(2) SR-IOV Resource/Initialization/Event Management
(3) PCI Express Basics
(4) Verification of PCIe from Implementation to Initial Operation |
| 11:00 am - 12:00 pm |
(1) PCIe 2.0 PHY Logical Sub-Block
(2) Single Root IOV Configuration
(3) Conventional PCI
(4) Predictable Compliance Verification Closure |
| 12:00 pm - 1:30 pm |
Lunch and Exhibit |
| 1:30 pm - 2:30 pm |
(1) PCIe 2.0 Cards and Slots
(2) Multi-Root IOV - Part 1
(3) PCI Express Cabling
(4) Integration and System Verification of PCIe IP |
| 2:30 pm - 3:30 pm |
(1) PCIe 2.0 Compliance Requirements
(2) Multi-Root IOV - Part 2
(3) Reliable Data Transmission Features of PCI Express
(4) Understanding Jitter in System |
| 3:30 pm - 4:00 pm |
PM Break and Exhibit |
| 4:00 pm - 5:00 pm |
(1) PCIe 2.0 Signal Integrity Considerations
(2) Congestion / Quality of Service (IOV)
(4) PCIe 2.0 Server Validation Challenges
(4) Mastering Physical Layer Compliance Challenges at 5GT/s |
| 5:00 pm - 6:00 pm |
(1) PCIe 2.0 Software and Configuration Updates
(3) PCIe 2.0 Compliance Tools Demonstration
(4) Single Root IOV Endpoint Implementation |
| 6:00 pm - 8:00 pm |
Evening Mixer and Annual Member Meeting |
