PCI-SIG^® Developers Conference 2007
May 21-22, 2007

Presentations

PCI Express^® (PCIe^®)

PCIe 2.0 PHY Electrical Sub-Block - Part 1 & 2

PCIe 2.0 PHY Logical Sub-Block

PCIe 2.0 Cards and Slots

PCIe 2.0 Compliance Requirements

PCIe 2.0 Signal Integrity Considerations

PCIe 2.0 Software and Configuration Updates

PCIe 2.0 Compliance Tool Demonstrations

I/O Virtualization

IOV Architecture Overview 

SR-IOV Resource/Initialization/Event Management

Single Root IOV Configuration

Multi-Root IOV - Part 1 & 2

Congestion/Quality of Service

Introductory PCI Technology

PCI-SIG Architecture Overview

PCI Express Basics

Conventional PCI

PCI Express Cabling

Reliable Data Transmission Features of PCI Express

Members Implementation

PCIe as a Multiprocessor System Interconnect

Verification of PCIe IP from Implementation to Initial Operation

Predictable Compliance Verification Closure

Integration and System Verification of PCIe IP

Understanding Jitter in System

Mastering Physical Layer Compliance Challenges at 5GT/s

PCIe 2.0 Server Validation Challenges

Single Root IOV Endpoint Implementation

Common Pitfalls in PCIe 2.0 Migration

PCIe Core Verification Using Random Error Injection

Minimizing PCI Express Power Consumption

Cosimulation of PCIe PHYs

Verification of Advanced Error Handling Architecture

Guidelines for High-Speed PHY Integration, Debug and Test

Cabled PCI Express - Implementation Considerations

LTSSM Implementation at 5GT/s and Beyond