| Time |
Title |
| 8:00 am - 9:00 am |
Registration in Foyer |
| 9:00 am - 10:00 am |
(1) PCIe 3.0 Electricals - Part I
(2) Introduction to IOV - Part I
(3) PCI-SIG Architecture Overview
(4) Advanced PCIe Features - Implementation Considerations |
| 10:00 am - 11:00 am |
(1) PCIe 3.0 Electricals - Part II
(2) Introduction to IOV - Part I
(3) PCI Express Basics
(4) Protocol Analysis Methodologies of Deadlock Scenarios |
| 11:00 am - 12:00 pm |
(1) PCIe 3.0 Electricals - Part III
(2) Address Translation Services
(3) Conventional PCI
(4) Understanding PCIe 2.0 Bandwidth Management |
| 12:00 pm - 1:30 pm |
Lunch and Exhibit |
| 1:30 pm - 2:30 pm |
(1) PCIe Protocol Updates - Part I
(2) Single Root IOV
(4) 5 GT/s and 8 GT/s PCIe Compared
(4) PCIe 2.0 Link Layer Test Concepts |
| 2:30 pm - 3:30 pm |
(1) PCIe Protocol Updates - Part II
(2) Multi-Root IOV - Part I
(4) Challenges in Design and Verification of PCIe Cores
(4) PCI Express and MR-IOV: Maximizing Multi-Processor Systems |
| 3:30 pm - 4:00 pm |
PM Break and Exhibit |
| 4:00 pm - 5:00 pm |
(1) PCIe Electromechanical Updates
(2) Multi-Root IOV - Part II
(4) Fixture Compensation in PCIe Signal Integrity Management |
| 5:00 pm - 6:00 pm |
(1) PCIe 2.0 Compliance and Interoperability
(4) Signal Integrity Challenges and Design Practices on Mobile Platforms |
| 6:00 pm - 8:00 pm |
Evening Mixer and Annual Member Meeting |
