PCI-SIG - Agenda

PCI-SIG Developers Conference 2008 Agenda

The sessions below are categorized by track subject according to the following key:

(1) PCI Express
(2) I/O Virtualization
(3) Introductory PCI Technology
(4) Members Implementation

Day One - Wednesday, June 11, 2008

Time	Title
8:00 am - 9:00 am	Registration in Foyer
9:00 am - 10:00 am	(1) PCIe 3.0 Electricals - Part I (2) Introduction to IOV - Part I (3) PCI-SIG Architecture Overview (4) Advanced PCIe Features - Implementation Considerations
10:00 am - 11:00 am	(1) PCIe 3.0 Electricals - Part II (2) Introduction to IOV - Part II (3) PCI Express Basics (4) Protocol Analysis Methodologies of Deadlock Scenarios
11:00 am - 12:00 pm	(1) PCIe 3.0 Electricals - Part III (2) Address Translation Services (3) Conventional PCI (4) Understanding PCIe 2.0 Bandwidth Management
12:00 pm - 1:30 pm	Lunch and Exhibit
1:30 pm - 2:30 pm	(1) PCIe Protocol Updates - Part I (2) Single Root IOV (4) 5 GT/s and 8 GT/s PCIe Compared (4) PCIe 2.0 Link Layer Test Concepts
2:30 pm - 3:30 pm	(1) PCIe Protocol Updates - Part II (2) Multi-Root IOV - Part I (4) Challenges in Design and Verification of PCIe Cores (4) PCI Express and MR-IOV: Maximizing Multi-Processor Systems
3:30 pm - 4:00 pm	PM Break and Exhibit
4:00 pm - 5:00 pm	(1) PCIe Electromechanical Updates (2) Multi-Root IOV - Part II (4) Fixture Compensation in PCIe Signal Integrity Management
5:00 pm - 6:00 pm	(1) PCIe 2.0 Compliance and Interoperability (4) Signal Integrity Challenges and Design Practices on Mobile Platforms
6:00 pm - 8:00 pm	Evening Mixer and Annual Member Meeting

Day Two - Thursday, June 12, 2008

Time	Title
9:00 am - 10:00 am	(1) PCIe 3.0 Electricals - Part I (2) Introduction to IOV - Part I (3) PCI-SIG Architecture Overview (4) Case Studies of Difficult Scenarios in Functional Verification
10:00 am - 10:30 am	AM Break and Exhibit
10:30 am - 11:30 am	(1) PCIe 3.0 Electricals - Part II (2) Introduction to IOV - Part II (3) PCI Express Basics (4) Citius, Altius, Fortius: Three Steps Towards PCIe 2.0 Success
11:30 am - 12:30 pm	(1) PCIe 3.0 Electricals - Part III (2) Address Translation Services (3) Conventional PCI (4) Negative Testing
12:30 pm - 1:30 pm	Lunch and Exhibit
1:30 pm - 2:30 pm	(1) PCIe Protocol Updates - Part I (2) Single Root IOV (4) Multicast PCI Express (4) Transmitter De-emphasis for PCI Express 2.0 Low-Swing Mode
2:30 pm - 3:30 pm	(1) PCIe Protocol Updates - Part II (2) Multi-Root IOV - Part I (4) Designing High Speed Transceivers for PCIe 2.0 and Beyond
3:30 pm - 4:00 pm	PM Break in Foyer
4:00 pm - 5:00 pm	(1) PCIe Electromechanical Updates (2) Multi-Root IOV - Part II (4) Using PCIe Over Cable for High-Speed CPU-to-CPU Communications
5:00 pm - 6:00 pm	(1) PCIe 2.0 Compliance and Interoperability

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