PCI-SIG - DevCon 2010 Agenda

PCI-SIG DevCon 2010

PCI-SIG Developers Conference 2010 Agenda

The sessions below are categorized by track subject according to the following key:

(1) PCI Express
(2) PCI-SIG Architecture
(3) Members Implementation

Day One - Wednesday, June 23, 2010

Time	Title
8:00 am - 9:00 am 9:00 am - 9:30 am	Registration in Foyer Introductory Keynote / Annual Member Meeting
9:30 am - 10:30 am	(1) PCIe 2.1 / PCIe 3.0 Protocol Changes (2) PCI-SIG Architecture Overview (3) PCI Express Advanced Signaling Analysis
10:30 am - 11:30 am	(1) PCIe PHY Logical (2) PCI Express Electrical Basics (3) Experiences and Insights Verifying PCI Express Cores
11:30 am - 1:00 pm	Lunch and Exhibit
1:00 pm - 2:00 pm	(1) PCIe 3.0 Electricals - Part I (2) IOV Overview (3) Compliance and Interoperability Testing Before and After
2:00 pm - 3:00 pm	(1) PCIe 3.0 Electricals - Part II (2) PCIe 3.0 Overview (3) 5GT/s and Other Considerations for Cabled PCIe
3:00 pm - 3:30 pm	PM Break and Exhibit
3:30 pm - 4:30 pm	(1) PCIe 3.0 Cards (2) PCI Express Basics (3) The Case for PCIe on the Backplane
4:30 pm - 5:30 pm	(1) PCIe 3.0 Compliance (2) PCIe 2.x vs. PCIe 1.x (3) Impact of Halogen-Free PCB Material on PCIe Signaling
5:30 pm - 7:00 pm	Evening Mixer

Day Two - Thursday, June 24, 2010

Time	Title
9:00 am - 10:00 am	(1) PCIe 2.1 / PCIe 3.0 Protocol Changes (2) PCI-SIG Architecture Overview (3) PCI Express 3.0 PHY Implementation Challenges at 8GT/s
10:00 am - 10:30 am	AM Break and Exhibit
10:30 am - 11:30 am	(1) PCIe 3.0 Electricals - Part I (2) PCI Express Basics (3) Avoiding Common Link and Transaction Layer Problems
11:30 am - 12:30 pm	(1) PCIe 3.0 Electricals - Part II (2) IOV Overview (3) Gotchas in PCIe Implementation beyond 5GT/s
12:30 pm - 1:30 pm	Lunch and Exhibit
1:30 pm - 2:30 pm	(1) PCIe 3.0 Cards (2) PCIe 3.0 Overview (3) Characterizing PCI Express Lanes with Channel Degradation
2:30 pm - 3:30 pm	(1) PCIe PHY Logical (2) PCI Express Electrical Basics (3) Exhaustive Pre-silicon Verification of PCIe
3:30 pm - 4:00 pm	PM Break in Foyer
4:00 pm - 5:00 pm	(1) PCIe 3.0 Compliance (2) PCIe 2.x vs. PCIe 1.x (3) Mitigate the Verification Effort when Moving beyond PCIe 2.x

Sponsors