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PCI Express® and MIPI® M-PHY® Specifications
Frequently Asked Questions
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Questions
Q: Why is PCI-SIG adapting PCIe protocols to operate over the MIPI M-PHY specification?
Q: Is there a name for the PCIe adaptation that operates with the MIPI M-PHY?
Q: PCIe technology is in every server, workstation and laptop PC. Why is PCIe over M-PHY a suitable I/O technology for tablet and smartphone devices?
Q: What is the primary benefit of using PCIe architecture with the MIPI M-PHY?
Q: What are the main applications of the PCIe adaptation on the MIPI M-PHY?
Q: Is there a need for new software to support the PCIe adaptation on the MIPI M-PHY?
Q: When and how will the PCI-SIG release the PCIe adaptation layer specification?
Answers
Why is PCI-SIG adapting PCIe protocols to operate over the MIPI M-PHY specification?
A: As PCs become lighter and thinner and tablets and smartphones become more functional, consumers want seamless, always on/always connected functionality from their computing devices. To respond to these market expectations, device manufacturers need efficient, intelligent I/O technologies. The PCIe architecture satisfies all of these requirements, and with the adaptation to operate over the M-PHY specification it can deliver consistent high performance in power-constrained platforms such as ULT laptops, tablets and smartphones. By delivering this technology, the PCI-SIG is meeting the emerging needs of its members and the industry.
Q: Is there a name for the PCIe adaptation that operates with the MIPI M-PHY?
A: The PCI-SIG has recently accepted this technology as a contribution from its members and will soon announce a suitable name for it.
Q: PCIe technology is in every server, workstation and laptop PC. Why is PCIe over M-PHY a suitable I/O technology for tablet and smartphone devices?
A: As a broadly adopted technology standard, PCIe benefits from several decades of innovations with universal support in all major Operating Systems, a robust device discovery and configuration mechanism, and comprehensive power management capabilities that very few, if any, of the other I/O technologies can match. PCIe technology has a flexible, layered protocol that enables innovations to occur at each layer of the architecture independent of the other layers. In this way, power-efficient PHY technologies, such as MIPI M-PHY, can be integrated with the familiar and highly functional PCIe protocol stack to deliver best-in-class and highly scalable I/O performance in tablet and smartphone devices.
Q: What is the primary benefit of using PCIe architecture with the MIPI M-PHY?
A: This collaboration will enable component and device manufacturers to take advantage of the reduction in I/O technology proliferation, allowing them to reduce their product development time, product validation time and significantly increase their time to market. The mobile and handset industry can realize these benefits today by adopting PCIe architecture adapted to run over M-PHY.
Q: What are the main applications of the PCIe adaptation on the MIPI M-PHY?
A: The initial application of this technology is anticipated to be high-performance wireless communications with other applications based on device design requirements. Future implementations are expected in the handheld device market, including smartphones, tablets and other ultra-low power applications. As a power-efficient, general-purpose load-store I/O architecture, component and device designers can implement this technology in other I/O expansion usage models of their choosing as well.
Q: Is there a need for new software to support the PCIe adaptation on the MIPI M-PHY?
A: This adaptation of the PCIe architecture requires no new software. It reuses the existing, ubiquitous support in all major Operating Systems (e.g. pci.sys bus driver on Windows platforms). This includes existing support for device discovery, configuration and control.
Q: When and how will the PCI-SIG release the PCIe adaptation layer specification?
A: The PCI-SIG will deliver this technology as an extension to the existing PCIe 3.0 Base specification via ECN by the end of 2012. This technology will be fully integrated into the next release of the PCIe Base specification, PCIe 4.0, enabling ease of access and reference.
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