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PCI-X 2.0 Frequently Asked Questions

Questions

Q: How are PCI-X™ versions 1.0 and 2.0 related to PCI™? Are they the same?

Q: What speed grades are in the PCI-X 2.0 specification?

Q: Is PCI-X 2.0 backward compatible with all generations of PCI?

Q: What features are introduced in the PCI-X 2.0 specification?

Q: What are the target applications for PCI-X 266 and PCI-X 533?

Q: How can the 16-bit versions of PCI-X be used?

Q: Does PCI-X 2.0 support only point-to-point loads? Or, does it support multi-drop too?

Q: PCI-X 533 electrical parameters appear as “design goals” in the specification. What does this mean, and when will the final numbers be released?

Q: Why is the time-to-market for PCI-X 266 and PCI-X 533 shorter than that of other technology transitions?

Q: Why does PCI-X 2.0 provide such cost-effective bandwidth?

Q: How can I get a copy of the PCI-X 2.0 specification?

Answers

Q: How are PCI-X versions 1.0 and 2.0 related to PCI? Are they the same?
A: PCI-X 2.0 is the next generation of PCI. It builds upon previous generations of PCI including the electricals, protocols, signals names and functions, connectors, etc. It also maintains backward compatibility with conventional PCI. It is the next logical advance in the world’s most popular PC bus. There have been many generations of PCI, which all build upon each other. The PCI bus began with a 32-bit / 33MHz specification. Over time, to increase performance, 64-bit and 66MHz versions were introduced. To increase the bus speed and reduce latency PCI-X 1.0 was developed, with a maximum clock speed of 133 MHz. PCI-X 1.0 also introduced improved protocols, such as the split-transaction protocol which allows more efficient use of bus bandwidth, resulting in throughput gains beyond the simple increases in clock speed and bus width. Because of the demand for even higher throughput and to improve error correction, the PCI-X 2.0 specification was developed. It extends the bus frequency to 266 MHz and 533MHz and adds advanced features like Error Code Correction (ECC), while still maintaining backward compatibility to the first generation.

Q: What speed grades are in the PCI-X 2.0 specification?
A: There are four speed grades in the PCI-X 2.0 specification: PCI-X 66, PCI-X 133, PCI-X 266, and PCI-X 533. The PCI-X 66 and PCI-X 133 speed grades were included in the PCI-X 1.0 specification; they support 66MHz, and 133MHz PCI-X respectively. 100MHz PCI-X has been implemented in the market by using PCI-X 133 adapter cards. Both PCI-X 266 and PCI-X 533 are new to PCI-X 2.0; they are the 266MHz and 533MHz versions of the specification. All four speed grades are included in the PCI-X 2.0 specification.

Q: Is PCI-X 2.0 backward compatible with all generations of PCI?
A: Yes. PCI-X 2.0 is logically backward compatible to all previous generations and speed grades of PCI and PCI-X. PCI-X 266 and PCI-X 533 devices are electrically compatible with 3.3V and 1.5V IO buffers only; they are not compatible with 5V PCI.

Q: What features are introduced in the PCI-X 2.0 specification?
A: The PCI-X 2.0 specification introduces features such as Error Correction Code (ECC), 1.5V signaling, source-synchronous strobes, device ID messages, and a 16-bit version. The ECC improves the robustness of the interface. Likewise, the 1.5V signaling and strobes improve the performance so that the bus can run at 533MHz. Device ID messages are designed to enable a whole new class of peer-to-peer transfer applications. The 16-bit version of the bus is designed for embedded applications where bandwidth can be traded-off to reduce device pin counts.

Q: What are the target applications for PCI-X 266 and PCI-X 533?
A: The target applications for PCI-X 2.0 technology are the workstation and server segments of the computer industry.

Q: How can the 16-bit versions of PCI-X be used?
A: The 16-bit application of PCI-X is uniquely suited for applications that require a reduced cost interface. The 16-bit functionality can be implemented either by creating a stand-alone 16-bit bus, or by breaking a 64-bit bus into four different segments of 16-bits each. For example, a peer-to-peer bridge with a 64-bit PCI-X 533 interface on its secondary side could alternatively implement four independent buses, each 16 bits wide, to support four independent loads each running at 533MHz. This capability may be particularly interesting for embedded applications.

Q: Does PCI-X 2.0 support only point-to-point loads? Or, does it support multi-drop too?
A: PCI-X 2.0 supports both point-to-point loads and multi-drop loads. A PCI-X bus running at 66MHz can support four card slots. A PCI-X bus running at 100MHz can support two slots (when using PCI-X 133 adapter cards). At higher speeds (PCI-X 133, PCI-X 266, and PCI-X 533) one slot is supported.

In embedded environments where components are soldered down and connectors aren’t used there exists the possibility for multiple loads at 133MHz. However, these electrical environments are not defined in the specification, since interoperability isn’t an issue in embedded applications. It is left to the user to validate multiple embedded loads at the higher clock frequencies.

Q: PCI-X 533 electrical parameters appear as “design goals” in the specification. What does this mean, and when will the final numbers be released?
A: The PCI-X Electrical and Mechanical Specification includes fully validated and released parameters for PCI-X 266 and “design goals” for PCI-X 533. “Design goals” have been fully validated to guarantee interoperability, but are not fully released. This allows for the possibility of further refinement of the PCI-X 533 design parameters to improve manufacturing yields. 

Q: Why is the time-to-market for PCI-X 266 and PCI-X 533 shorter than that of other technology transitions?
A: The transition to PCI-X 266 and PCI-X 533 is shorter than that of other technologies because it leverages and reuses much of the technology in the PCI-X 1.0 specification. The architecture, state machine, bus functional model, device drivers, signals and signal functionality, pin-outs, connector, test suites, form factors, layouts, and design tools are all either identical to PCI-X 1.0, or are highly leveraged.

Q: Why does PCI-X 2.0 provide such cost-effective bandwidth?
A: PCI-X 2.0 is highly cost-effective throughout the entire cost structure. PCI-X 2.0 uses very little silicon for its protocol engine and uses very little silicon for its physical interface. It requires minimal redesign from earlier versions of PCI, maintains the same low cost connector, uses similar design tools and testing methodology and equipment. It uses the same board form factor that has already been designed into previous systems and requires no new BIOS, device drivers, or operating systems. For high-bandwidth systems it maintains similar pin counts to serial technologies.

Q: How can I get a copy of the PCI-X 2.0 specification?
A: A benefit of membership in the PCI-SIG(R) is access to both published specifications and draft specifications (see membership benefits at: http://www.pcisig.com/membership/about_us/). The specification is also available for purchase by non-members. Current specifications can be obtained either through the PCI-SIG website.

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