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PCI Express

PCI Express® 2.0
Frequently Asked Questions

Questions

Q: How can I get a copy of the PCI Express (PCIe) 2.0 specification?

Q: What are the benefits of PCIe 2.0? What business opportunities does it bring to the market?

Q: Are both 2.5GT/s and 5GT/s signaling rates supported in the PCIe 2.0 specification?

Q: Is PCIe 2.0 backward compatible with PCIe 1.1 and 1.0?

Q: What other features are introduced in the PCIe 2.0 specification?

Q: What were the initial target applications for PCIe 2.0?

Q: What test tools and other infrastructure are available to support the development of PCIe 2.0 products?

Q: Where can interested parties get more information?

Answers

Q: How can I get a copy of the PCI Express (PCIe) 2.0 specification?
A: Visit www.pcisig.com to become a member and access the specification.

Q: What are the benefits of PCIe 2.0? What business opportunities does it bring to the market?
A: While doubling the bit rate satisfies high-bandwidth applications, faster signaling has the advantage of allowing various interconnect links to save cost by adopting a narrow configuration. For example, a PCI Express 1.1 x8 link (8 lanes) yields a total aggregate bandwidth of 4Gbps, which is the same bandwidth obtained from a PCI Express 2.0 x4 link (4 lanes) that adopts the 5GT/s signaling technology. This can result in significant savings in platform implementation cost while achieving the same performance level. Backward compatibility is retained as 2.5 GT/s adapters can plug into 5.0 GT/s slots and will run at the slower rate. Conversely, PCIe 2.0 adapters running at 5.0 GT/s can plug into existing PCIe slots and run at the slower rate of 2.5 GT/s.

Q: Are both 2.5GT/s and 5GT/s signaling rates supported in the PCIe 2.0 specification?
A: The PCIe Base 2.0 specification supports both 2.5GT/s and 5GT/s signaling rates, in order to retain backward compatibility with existing PCIe 1.0 and 1.1 systems. Aside from the faster bit rate, there are a number of improvements in this specification that allow greater flexibility and reliability in designing PCIe links. For example, the interconnect can be dynamically managed for platform power and performance considerations through software controls. Another significant RAS feature is the inclusion of new controls to allow a PCIe link to continue to function even when some lanes become non-operational.

Q: Is PCIe 2.0 backward compatible with PCIe 1.1 and 1.0?
A: Yes. The PCIe Base 2.0 specification supports both the 2.5GT/s and 5GT/s signaling technologies. A device designed to the PCIe Base 2.0 specification may support 2.5GT/s, 5GT/s or both. However, a device designed to operate specifically at 5GT/s must also support 2.5GT/s signaling. The PCIe Base specification covers chip-to-chip topologies on the system board. For I/O extensibility across PCIe connectors, the Card Electromechanical (CEM) and ExpressModule™ specifications will also need to be updated, but this work will not impact mechanical compatibility of the slots, cards or modules.

Q: What other features are introduced in the PCIe 2.0 specification?
A: The most predominant feature in PCIe 2.0 is 5GT/s speed, which includes new mechanisms for software control of link speed, reporting of speed and width changes, and control of loopback. Other new features include:

  • PCI compatibility using the established PCI software programming models, thus facilitating a smooth transition to new hardware while allowing software to evolve to take advantage of PCI Express features
  • Enhanced Completion Timeout Control, which includes required and optional aspects, reduces false timeouts and increases the ability to ‘tune’ the timeouts
  • Function Level Reset and Access Control Services, giving enhanced robustness and support of certain IOV features (optional)
  • Slot Power Limit Changes to allow for higher powered slots, which support the newer, high-performance graphics cards; this new feature works in tandem with the 300W Card Electro-mechanical specification
  • Speed Signaling Controls to enable software to determine whether a device can operate at a specific signaling rate, which can be used to reduce power consumption, as well as provide gross level I/O to memory

Q: What were the initial target applications for PCIe 2.0?
A: The same set of core applications, high-performance graphics, enterprise-class storage and high-speed networking that benefited from the introduction of PCIe 1.0 architecture have led the charge for adoption of PCIe 2.0.

Q: What test tools and other infrastructure are available to support the development of PCIe 2.0 products?
A: The established PCIe ecosystem delivers both pre-silicon and post-silicon tools to assist design engineers with implementing PCIe 2.0 products. In addition, PCI-SIG provides updated hardware test fixtures and test software upgrades to facilitate compliance verification at its Compliance Workshops.

Q: Where can interested parties get more information?
A: PCI-SIG is the sole source for PCIe specifications. In addition, both the PCI-SIG and its members provide a plethora of technical and marketing collateral in support of the PCIe architecture. Please visit www.pcisig.com for additional information.

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