PCI-SIG Technology

• Download a PDF version of this document (.9MB PDF)

PCI-X 2.0: The Next Generation for Backward-Compatible PCI

PCI-X 2.0 is an evolutionary, backward compatible technology that builds on the foundation of PCI and PCI-X 1.0b while offering bandwidths 4 times higher than PCI-X 1.0b without increasing pin-count. These new, higher bandwidths are ideal for future server-oriented adapter cards in the areas of Fibre Channel, RAID, networking, InfiniBand™ Architecture, SCSI, iSCSI, and other high-bandwidth technologies. The migration to PCI-X 2.0 is simplified by the fact that it is both hardware and software compatible with PCI-X 1.0b and PCI. PCI-X 2.0 design and implementation are also made easy because many elements of PCI-X 1.0b are retained. There are also hundreds of products currently available that can seamlessly connect with PCI-X 2.0. Some of the key features include:

• Doubles and Quadruples PCI-X 1.0b bandwidth.
• Full hardware and software backward compatibility to previous generations of PCI 1.0b.
• Builds upon tens of man-centuries of development.
• Uses the same form factor, pinouts, connector, bus widths, protocols, and electrical signaling.
• Enables 10Gb Ethernet, 10Gb Fibre Channel, InfiniBand™ Architecture, and other IO technologies.
• Full RAS support including ECC.
• Performance 32 times higher than the first generation of PCI.

PCI Express: Performance Scalability for the Next Decade

PCI Express (formerly 3GIO) is a new I/O technology that is compatible with the current PCI software environment. PCI Express defines a packetized protocol and a load/store architecture. Its layered architecture enables attachment to copper, optical, or emerging physical signaling media. PCI Express uses an embedded clocking scheme to enable better frequency scaling and provides many advanced features as well as innovative form factors. It can be used for chip-to-chip and add-in card applications to provide connectivity for adapter cards, as a graphics I/O attach point for increased graphics bandwidth, as well as an attach point to other interconnects like 1394b, USB 2.0, InfiniBand™ Architecture and Ethernet. Some of its key features include:

• Compatibility with PCI software model requiring no changes to current Operating Systems while maintaining platform configuration and device driver interfaces.
• Layered architecture enabling physical layer attachment to copper, optical, or emerging physical signaling media to allow for future encoding schemes
• High bandwidth per pin for enabling unique and small form factors, reducing cost, simplifying board design and routing, and reducing signal integrity issues.
• Embedded clocking scheme enables superior frequency scalability versus source synchronous clocking.
• Bandwidth scalability with frequency and/or interconnect width.
• Low pin count, point-to-point interconnect with packetized protocol and load-store architecture.
• Advanced features include: aggressive power management, QoS, isochrony, hot attach/detach, RAS, etc.
• Built on top of the existing PCI software model and supported by the PCI-SIG to enable broad industry adoption.

PCI Hot-Plug: Advancing PCI to Better Support Mission Critical Servers

PCI Hot-Plug allows the removal and insertion of devices without having to turn off a server, therefore maximizing uptime, and allowing IT managers to build in redundancy. The adoption of the specification is important for businesses that operate in mission-critical server environments. Today, PCI Hot-Plug is a "must have" for most server markets. To further expand the standard, the PCI-SIG has recently released the new PCI Standard Hot-Plug Controller and Subsystem Specification. This will help lower the cost of hot-plug systems and enable standard operating systems to include native support for PCI Hot-Plug. The PCI Hot-Plug Specification and the PCI Standard Hot-Plug Controller and Subsystem Specification are both available to PCI-SIG members and can be downloaded from www.pcisig.com.

PCI-X 1.0b: A High-performance Extension to the PCI Bus Architecture

PCI-X 1.0b is a backward compatible high-performance extension to the PCI Bus. PCI-X 1.0b is shipping today in servers that require higher bandwidth, with potential use in workstations.

Running at frequencies of up to 133 MHz at either 32-or 64-bit widths, PCI-X 1.0b is designed to bring the PCI Local Bus data throughput performance to over 1 Gbyte/second (8 Gbits/sec). PCI-X 1.0b brings more efficient bus operation, allowing easier interfacing with memory controllers, bridges and other advanced I/O solutions. Other details include:

• Split Transactions allow an initiator device to make only one data request and relinquish the bus, rather than constantly polling the bus for a response.
• Byte Count enables initiator to specify in advance the number of bytes requested, eliminating the inefficiency of speculative pre-fetches.
• Improved error handling allows recovery from some kinds of data parity errors
• Relaxed transaction ordering improves performance in complex multi-CPU systems and in real-time applications

The PCI-X 1.0b specification is available to PCI-SIG members and can be downloaded from www.pcisig.com.

PCI 2.3 - An Evolution of the Conventional PCI Specification

Revision 2.3 is an evolutionary change to the PCI Local Bus Specification. Revision 2.3 makes a significant step in migrating the PCI bus from the original 5.0 volt signaling, to a 3.3 volt signaling bus. Revision 2.3 supports the 5V and 3.3V keyed system board connectors (as did revision 2.2) but revision 2.3 supports only the 3.3V and Universal keyed add-in cards. The 5V keyed add-in card is not supported in revision 2.3. PCI 66, PCI-X 1.0b, Mini PCI, and Low Profile PCI support only 3.3 volt signaling on 3.3V keyed system board connectors and 3.3V and Universal keyed add-in cards.

High performance technologies power the logic within the chips with 3.3 or lower voltages. The newer high performance technologies cannot support 5 volt compatible signaling on the off-chip drivers. As a result, the host bridge needs to migrate to 3.3 volt signaling with 3.3V keyed system board connectors. Removing support for 5V keyed add-in cards is the first step in the migration to 3.3 volt signaling systems and ensures revision 2.3 compliant add-in cards will be usable in 3.3V keyed system board connectors.

In addition to the changes described above, revision 2.3 also incorporates other ECNs and approved errata. Revision 2.3 PCI Local Bus Specification is available to PCI-SIG members and can be downloaded from www.pcisig.com.

PCI-SIG - A Leading Standards Organization

Formed in 1992, the PCI-SIG is the organization that develops and manages what has become one of the most successful I/O bus standards, the PCI Local Bus specification. Through wide industry support and active developer participation, the PCI Local Bus specification has been a well-maintained, open and non-proprietary solution that is scalable and retains legacy compatibility for today's applications. In addition to the advancement of the PCI specification, the PCI-SIG educates the industry on the latest developments of the PCI Local Bus through technical seminars. The Compliance Workshops (Plugfests) provide forums for testing of interoperability of the many PCI-related systems and software in the market. The PCI-SIG has continued to develop successful extensions to the PCI Local Bus, such as PCI-X 1.0b and Mini PCI, as industry needs evolve. For information on how to become a member of the PCI-SIG go to www.pcisig.com.