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- pci to pci bridge in NT4.0
- From: vision <vision@public3.bta.net.cn>
- BAR set to 0 - all the bits have to be 0, right?
- RE: what is put in Vendor ID and Device ID?
- From: Dave New <NewD@esi.com>
- what is put in Vendor ID and Device ID?
- From: Mark Galecki <marek@greenspring.com>
- subscribe
- From: "xie zhonghui" <gzxxzzhh@public1.guanghzhou.gd.cn>
- Re: PCI Card Clock Trace Length
- From: Ivor Bowden <ivor@peritek.com>
- Re: PCI Card Clock Trace Length
- From: Richard Walter <rwalter@corp.auspex.com>
- PCI Card Clock Trace Length
- From: Frank Walker <frank_walker@bigfoot.com>
- RE: PCI Request
- From: Brooks Lame <Brooks_Lame@mcg.mot.com>
- Re: AW: PCI signal integrity
- From: Ivor Bowden <ivor@peritek.com>
- PCI Request
- subscribe
- From: Richard Tuck <richard@quadrics.com>
- RE: Universal PCI signaling
- From: Andrew Ingraham <Andrew.Ingraham@digital.com>
- AW: PCI signal integrity
- From: "Lange, Michael" <lange@dvs.de>
- RE: PMC BUSMODE#1
- From: Brooks Lame <Brooks_Lame@mcg.mot.com>
- Re: PMC BUSMODE#1
- From: Ivor Bowden <ivor@peritek.com>
- RE: PCI signal integrity problem on passive PCI backplanes
- From: Brooks Lame <Brooks_Lame@mcg.mot.com>
- PCI signal integrity problem on passive PCI backplanes
- From: "Lange, Michael" <lange@dvs.de>
- ISA Retainer
- From: Neil Watkinson <neil@stonemicro.com.au>
- Universal PCI signaling
- From: John Hutchins <jhutchins@etsolution.com>
- PMC BUSMODE#1
- From: Tai Phan <phan@Iphase.COM>
- subscribe
- From: Sudhirranjan Proch <sudhiranjan@dcmds.co.in>
- subscribe
- From: Rajat Gupta <rajatg@dcmds.co.in>
- Unidentified subject!
- From: "Lange, Michael" <lange@dvs.de>
- PCI Interrupts
- From: Richard Collins - reDSP <redsp@usa.net>
- PCI-to-PCI Bridge Architecture Specification Announcement
- From: "Comins, Todd" <todd.comins@intel.com>
- PCI version compatibility and video card question
- From: "David Schneider" <herblisa@ultinet.net>
- [Fwd: Message Signaled Interrupts]
- From: Jim Freeman <jfreeman@plxtech.com>
- rev 2.1 base classes and sub classes
- From: Chris Roussel <croussel@broadcom.com>
- ANNOUNCE: A new logic simulation library with PCI models
- From: udif@usa.net (Udi Finkelstein)
- Questions about PCI-X FAQ
- From: "Eric Rehm" <eric@equator.com>
- PCI 2.1, Fig 4-5 and notes for Table 4-6
- From: Ruchi_Wadhawan@3com.com
- Embedded PCI market data
- From: Kent Dahlgren <kent@dahlgren.to>
- PCI SIG News Flash
- From: Richard Baek <rbaek@vtm-inc.com>
- Re: Galileo GT 64011 + PC BIOS Extension
- From: "John R Pierce" <pierce@hogranch.com>
- Galileo GT 64011 + PC BIOS Extension
- From: "Finichiu György" <finisch@freemail.c3.hu>
- Pullup Resistor Values in PCI 2.1 Spec
- From: "O'Shea, David J" <david.j.oshea@intel.com>
- PCI Config. Utility
- From: "Yousef Vazir" <yousefv@initio.com>
- PCI-X
- From: Richard Baek <rbaek@vtm-inc.com>
- 3.3V Device driving a 5V Bus
- From: Andrew Stone <andrews@met.crc.org.au>
- AMCC pass through problem??
- From: Tom Stamp <TomS@Optiscan.com.au>
- subscribe
- From: Dave Barrett <Dave.Barrett@intel.com>
- Taiwan PCI Compliance Workshop and Conference
- From: Richard Baek <rbaek@vtm-inc.com>
- Re: pci extensions (was: *New* PCI bus standard?)
- From: "John R Pierce" <pierce@hogranch.com>
- More details : *New* PCI bus standard
- From: sriram@neomagic.com (Sriram Ramamurthy)
- Re: PC with a 64-bit 33MHz slot??
- From: "John R Pierce" <pierce@hogranch.com>
- Re: pci extensions (was: *New* PCI bus standard?)
- From: Mike Dini <mdini@dinigroup.com>
- Re: pci extensions (was: *New* PCI bus standard?)
- From: "Jeff DiNapoli" <jmd@audio2.engr.sgi.com>
- Re: pci extensions (was: *New* PCI bus standard?)
- From: "Jeff DiNapoli" <jmd@audio2.engr.sgi.com>
- MiniPCI
- From: Isaac Livny <iml@mtm3.ho.lucent.com>
- RE: pci extensions (was: *New* PCI bus standard?)
- From: Andrew Ingraham <Andrew.Ingraham@digital.com>
- RE: pci extensions (was: *New* PCI bus standard?)
- From: Andrew Ingraham <Andrew.Ingraham@digital.com>
- RE: pci extensions (was: *New* PCI bus standard?)
- From: Brooks Lame <Brooks_Lame@mcg.mot.com>
- Re: pci extensions (was: *New* PCI bus standard?)
- From: Alan Deikman <Alan.Deikman@znyx.com>
- PC with a 64-bit 33MHz slot??
- From: Ed Romascan <ed@magma.COM>
- Re: Bus Clock Speed
- From: Steven Larky <larky@anchorchips.com>
- RE: PCI card on other side of bridge
- From: "Schneider, Dave" <David.Schneider@emulex.com>
- Re: Bus Clock Speed
- From: "John R Pierce" <pierce@hogranch.com>
- subscribe
- From: Henia Senet-Larson <henia.senet_larson@ocegr.fr>
- RE: Capacitors on Power Pins - a nit
- From: Andrew Ingraham <Andrew.Ingraham@digital.com>
- Re: Bus Clock Speed
- From: Ivor Bowden <ivor@peritek.com>
- RE: PCI card on other side of bridge
- From: "Schneider, Dave" <David.Schneider@emulex.com>
- pci extensions
- From: Darrel Peterson <DPeterson@mapletreenetworks.com>
- Bus Clock Speed
- From: Richard Collins - reDSP <redsp@usa.net>
- subscribe
- From: Henia Senet-Larson <henia.senet_larson@ocegr.fr>
- RE: Capacitors on Power Pins
- From: David Black <DavidB@anchorchips.com>
- Re: PCI card on other side of bridge
- From: Graeme Gill <graeme@colorbus.com.au>
- Capacitors and VIO clamp
- From: "William Benner" <william_benner@email.msn.com>
- RE: what is pci mezzanine card?
- From: Brooks Lame <Brooks_Lame@mcg.mot.com>
- Re: Capacitors on Power Pins
- From: Bob Mathews <bobm@lsil.com>
- Capacitors on Power Pins
- From: "William Benner" <william_benner@email.msn.com>
- subscribe
- From: engelbregt@igr.nl (Johann Engelbregt)
- PCI card on other side of bridge
- From: <richards@primary-image.com>
- Re: no PCIRST# !!! on IBM 340 with SiS computers ???
- From: wen-king@myri.com (Wen-King Su)
- Unidentified subject!
- From: "Alexander Vasilevich" <vasil@grsu.grodno.by>
- no PCIRST# !!! on IBM 340 with SiS computers ???
- From: Yaron Haviv <yaronh@voltaire.co.il>
- what is pci mezzanine card?
- From: "zgsun@nudt.edu.cn" <zgsun@nudt.edu.cn>
- pci bus coprocessors
- From: David Feustel <feustel@ix.netcom.com>
- *New* PCI bus standard?
- From: Alan Deikman <Alan.Deikman@znyx.com>
- RE: Mailing list 'Reply-To' header, anon submissions
- From: Brooks Lame <Brooks_Lame@mcg.mot.com>
- RE: 3.3V / 5V PCI
- From: Brooks Lame <Brooks_Lame@mcg.mot.com>
- RE: Responsibilty for enabling bus master enable bit?
- From: Brooks Lame <Brooks_Lame@mcg.mot.com>
- RE: Responsibilty for enabling bus master enable bit?
- From: "O'Shea, David J" <david.j.oshea@intel.com>
- Re: 3.3V / 5V PCI
- From: Quinn_Kunz@mtn.3com.com
- RE: 3.3V / 5V PCI Question
- From: Andrew Ingraham <Andrew.Ingraham@digital.com>
- 3.3V / 5V PCI
- From: "William Benner" <william_benner@email.msn.com>
- subscribe
- From: Uma Vadlakonda <#uvadlako@ix.netcom.com>
- 3.3V / 5V PCI Question
- From: "William Benner" <william_benner@email.msn.com>
- Demand mode DMA on the 960RP
- From: 471034N@knotes.kodak.com
- Responsibilty for enabling bus master enable bit?
- From: Richard Walter <rwalter@corp.auspex.com>
- Re: pci bus latency
- From: Graeme Gill <graeme@colorbus.com.au>
- pci bus latency
- From: "Joe Hanes" <joe_hanes8@hotmail.com>
- subscribe
- From: "jim.hoff" <hoff@aloft.micro.lucent.com>
- RE: 3.3V PCI PC's for Test
- From: Brooks Lame <Brooks_Lame@mcg.mot.com>
- 64-bit PCI bus
- From: Ganesan Viswanathan <ganesanv@ami.com>
- 3.3V PCI PC's for Test
- From: Quinn_Kunz@mtn.3com.com
- PCI add-in card: BIOS and driver questions
- From: Daniele Pinto <pinto@space.it>
- Unknown PCI signal PCI_PME, HELP !!!
- From: Olivier Auberson <Olivier.Auberson@merging.com>
- Re: Max retry ECR (fwd)
- From: Russ Herrell <russ@herrell.fc.hp.com>
- Stop during snoop
- From: Anders Enggaard <anderse@lsil.com>
- subscribe
- From: "Zbigniew Milczarek" <milzbign@lodz.pdi.net>
- PCI training hardware
- Re: Max retry ECR
- CRYSTAL OSCILLATORS
- From: "hankyungtelecom" <hank@hankyungtelecom.co.kr>
- subscribe
- From: William Wu <wwu@sebringring.bjt.com>
- subscribe
- From: Mike Smith <msmith@cognex.com>
- RE: basic doubts in PCI (re-send)
- From: Andrew Ingraham <Andrew.Ingraham@digital.com>
- Does this chip exist?
- From: Eric Goodill <ericg@cisco.com>
- Supply/ground pads for PCI I/Os
- From: Chris Tann <ctann@atmel.com>
- RE: basic doubts in PCI
- From: "Hazzah, Karen" <KHazzah@melita.com>
- basic doubts in PCI
- From: HEAD/TSD <ecilcmg@hd1.vsnl.net.in>
- Method for Partial Configuration (Was: Re[2]: BAR value of zero?)
- From: Richard Walter <rwalter@corp.auspex.com>
- RE: BIOS and Clocks
- From: Cédric Caron <Cedric.Caron@merging.com>
- [Q]Win-NT PCI Driver Book?
- From: "ÀåÁØ¿µ" <jyjang@daisy.ce.pusan.ac.kr>
- BIOS and Clocks
- From: "Terje Melsom, VMETRO" <terje@vmetro.no>
- Tval Measurement
- From: Adam Chen <achen@plxtech.com>
- Re: BAR value of zero?
- From: Richard Walter <rwalter@corp.auspex.com>
- PCI-to-HOTLink Card
- From: "Yazbek, Dan" <dyazbek@analogic.com>
- RE: BAR value of zero?
- From: Tom Hicks <thicks@fore.com>
- RE: BAR value of zero?
- From: Brooks Lame <Brooks_Lame@mcg.mot.com>
- Re: PCI-ISA Adaptor
- From: Mike Salameh <mike_salameh@plxtech.com>
- BAR value of zero?
- From: Erin Hunter <Erin_Hunter@spectrumsignal.com>
- subscribe
- From: Jeff <jmd@cthulhu.engr.sgi.com>
- subscribe
- From: "Keith F. Jasinski, Jr." <jasinski@mortara.com>
- Re: off the shelf PCI chips
- From: Dave Mitteer <davem@amcc.com>
- PMC 66 MHz EN
- From: Tai Phan <phan@Iphase.COM>
- Unidentified subject!
- From: Ed Healy <edh@sequent.com>
- Unsubscribe
- From: noam@genie.terra.co.il
- Re: off the shelf PCI chips
- From: Michael Tresidder <tresidd@vcubed.com>
- off the shelf PCI chips
- From: garyk@xactinc.com (Gary Kidwell)
- Q: Power Management Spec
- From: subbarao@erd.epson.com (Arumilli Subbarao 12/08/95)
- P2P and Windows NT
- From: Benoit Lemieux <Benoit.Lemieux@matrox.com>
- PCI 2.2 Draft
- From: gcw@aluxs.micro.lucent.com (Gary Wu)
- IDSEL with Config type 1
- From: Tai Phan <phan@Iphase.COM>
- PCI carrier board for PMC
- From: Gordon Brown <brown@signal.dera.gov.uk>
- Re: ~m
- From: "chefren" <chefren@pi.net>
- Roadmapper under C.1
- From: "Kaufman, Roger" <roger.kaufman@symbios.com>
- ~m
- From: "Philip Ronzone" <Philip.Ronzone@eng.efi.com>
- Re: target termination
- From: Joe Cowan <jpc@hpmckee.fc.hp.com>
- Re: BE/LE
- From: "chefren" <chefren@pi.net>
- RE: PCI Load Question
- From: Andrew Ingraham <Andrew.Ingraham@digital.com>
- Re: Hardware .vs. software?
- From: "John R Pierce" <pierce@hogranch.com>
- Processors and technology for PCI applications
- From: imshq <ims@dircon.co.uk>
- subscribe
- From: "¹Ú¸í¿µ" <mypark@trut.chungbuk.ac.kr>
- [Re: target termination]
- From: Michael Tresidder <tresidd@vcubed.com>
- PCI Load Question
- From: Todd Harrington <THarrington@TRILOGIC.com>
- BE/LE
- From: "Philip Ronzone" <Philip.Ronzone@eng.efi.com>
- Re: target termination
- From: Neal Palmer <neal@dinigroup.com>
- Re: Hardware .vs. software?
- From: "chefren" <chefren@pi.net>
- When SERR# should be deasserted?
- From: Takashi Nakamura <takashi_nakamura@yokogawa.co.jp>
- target termination
- From: Michael Tresidder <tresidd@vcubed.com>
- Hardware .vs. software?
- From: "Philip Ronzone" <Philip.Ronzone@eng.efi.com>
- Query..
- From: Dennis Healy <healy@bconnex.net>
- Re: Big and little endian issue
- From: "John R Pierce" <pierce@hogranch.com>
- Technical Information
- From: ERNESTO POISOT ORTIZ <EPOISOT@gomsa.com>
- Re: Big and little endian issue
- From: "chefren" <chefren@pi.net>
- RE: PCI Clock
- From: Chris Tann <ctann@atmel.com>
- subscribe
- From: asifk@sgp.amd.com (Asif Khan)
- RE: PCI Clock
- From: Richard Collins - reDSP <redsp@writeme.com>
- Unsubscribe
- From: noam@genie.terra.co.il
- subscribe
- From: Neeraj Gupta <neeraj@dcmds.co.in>
- BE & LE hardware help
- From: "Philip Ronzone" <Philip.Ronzone@eng.efi.com>
- Good design recognition
- From: "Philip Ronzone" <Philip.Ronzone@eng.efi.com>
- Bus parking protocols for Intel bridge chip sets
- From: Mark Valley <mark.valley@analog.com>
- ~m
- From: "Philip Ronzone" <Philip.Ronzone@eng.efi.com>
- Re: Big and little endian issue
- From: Jochen Roth <jochen@znyx.com>
- DEC 21052 bridge and I/O space transactions
- From: Jim Stevens <jstevens@computerboards.com>
- PCI Device Number
- From: Scot Crowner <scrowner@drti.com>
- unsubscribe
- From: "Henry Lau" <hlau@ptsc.com>
- RE: PCI Clock
- From: Andrew Ingraham <Andrew.Ingraham@digital.com>
- RE: Q: Power Management Spec
- From: "Solomon, Gary" <gary.solomon@intel.com>
- subscribe
- From: "Gagrani, Kishore" <Kishore.Gagrani@PRICESystems.com>
- RE: Strange resource alocation
- From: Cédric Caron <Cedric.Caron@merging.com>
- Re: Big and little endian issue
- From: "John R Pierce" <pierce@hogranch.com>
- Re: Big and little endian issue
- From: Jochen Roth <jochen@znyx.com>
- Re: Big and little endian issue
- From: Jochen Roth <jochen@znyx.com>
- PCI Clock
- From: "Stephen L Pendergast" <spender@qtrd.cts.com>
- Q: Power Management Spec
- From: kimm@efficient.com (Kim Martin)
- subscribe
- From: "Jean-Charles HOUSSIER (Paris, FRA)" <jch@france.europe.mcd.mot.com>
- UNSUBSCRIBE
- From: "Reyes, Ed" <ereyes@bindview.com>
- subscribe
- From: asifk@sgp.amd.com (Asif Khan)
- Re: Strange resource alocation
- From: "Alistair Jackson" <alistair@oxsemi.com>
- Re: Big/Little Endian issues
- From: "David B. Gustavson" <dbg@SCIzzL.com>
- Rev 2.0 /2.1 State Machines
- From: Tony Goodfellow <tg@gsi-inc.com>
- Big/Little Endian issues
- From: anagaraj@assuredaccess.com (Ashwath Nagaraj)
- Re: Shared I/O address
- From: AJ Roberts <aj@plutotech.com>
- Strange resource alocation
- From: Cédric Caron <Cedric.Caron@merging.com>
- Re: Big and little endian issue
- From: "David B. Gustavson" <dbg@SCIzzL.com>
- Re: Shared I/O address
- From: Alan Deikman <Alan.Deikman@znyx.com>
- Re: Shared I/O address
- From: "John R Pierce" <pierce@hogranch.com>
- Re: Shared I/O address
- From: Steven Larky <larky@kirby.anchorchips.com>
- Re:PCI Microcontrollers
- From: "Dan-HMSI Shimizu"<dshimizu@hmsi.com>
- Re: Shared I/O address
- From: AJ Roberts <aj@plutotech.com>
- Re: Shared I/O address
- From: Jim Holeman <holeman@austx.tandem.com>
- PCI Microcontrollers
- From: "Tony G" <tonygd@earthlink.net>
- Be / Le
- From: "Philip Ronzone" <Philip.Ronzone@eng.efi.com>
- Re: Big and little endian issue
- From: "Philip Ronzone" <Philip.Ronzone@eng.efi.com>
- Re: Shared I/O address
- From: "John R Pierce" <pierce@hogranch.com>
- Shared I/O address
- From: Daniele Pinto <pinto@spice.it>
- Plunk & Burn
- From: Team4U@mailexcite.com
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