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- PMC blanking plates for VME front panels
- From: Hugh Tarver <hwt@transtech.co.uk>
- Two Arbiters in a bus
- From: Young-Moo Lee <ymlee@encore.kaist.ac.kr>
- pci
- From: scaramouche@vnet.IBM.COM
- PCI Expansion Hardware
- From: Chas Horvath <chas@isis.com>
- pci
- From: Breck Ricketts <breck@sound.net>
- Re: Help! AMCC S5933Q Compatibility Issue
- From: Ken Crocker <kcrocker@kcconsulting.com>
- Re: Help! AMCC S5933Q Compatibility Issue
- From: Ken Crocker <kcrocker@kcconsulting.com>
- Help! AMCC S5933Q Compatibility Issue
- From: Ken Crocker <kcrocker@kcconsulting.com>
- Multifunction device
- From: Ravi Ranganathan <Ravi_Ranganathan@neomagic.com>
- Re: 3.8 ns delay on CompactPCI clock
- From: Andy Ingraham <ingraham@wrksys.ENET.dec.com>
- Re[2]: PCI Trace Velocity
- From: Bruce Hanahan <bhanahan@ccmail.crosscomm.com>
- Re: PCI Trace Velocity
- From: Andy Ingraham <ingraham@wrksys.ENET.dec.com>
- No Subject
- From: "Luc Baticle" <baticle1@InfoRoute.CGS.Fr>
- Trouble Shooting A PCI Card
- From: Wm Mark Clifford <mclifford@s1.drc.com>
- Re: PCI Trace Velocity
- From: Lorne J Levinson <fhlevins@wicc.weizmann.ac.il>
- Power management
- From: Ali Najafi <alinajafi@simei.aztech.com.sg>
- PCI Trace Velocity
- From: YoelL@vcon.co.il (Yoel lavian)
- Unidentified subject!
- From: robertm@marte.cinv.iteso.mx (Roberto Medina)
- Mother Boards
- From: robertm@marte.cinv.iteso.mx (Roberto Medina)
- Re: PCI - x86 coprocessor board
- From: Dave New <den@aisinc.com>
- Hot swap
- From: Gene Glick <GGLI@dictaphone.com>
- How to know how much power a PCI card consume
- From: Pierre-Yves Santerre <pierreys@MICROSOFT.com>
- Windows NT and PPBs
- From: John Keefe <keefe@mrt.magma.COM.>
- re: Boot analysis from PCI
- From: frances_cohen@ptltd.com
- RE: REQ#/GNT# behavior at RST# deassertion
- From: "Kimmery, Clifford (FL51)" <kimmery@space.honeywell.com>
- REQ#/GNT# behavior at RST# deassertion
- From: kevin.normoyle@Eng.Sun.COM (Kevin Normoyle)
- Re: Simulating/verifying PCI bidir requirements
- From: bradshaw@nlc.com (Lee Bradshaw)
- Re: What's HRPCI ?
- From: Dave New <den@aisinc.com>
- Re: Simulating/verifying PCI bidir requirements
- From: danj@austx.tandem.com (Dan Joyce)
- What's HRPCI ?
- From: "David O'Shea" <daveo@corollary.com>
- Re: REQ#/GNT# behavior at RST# deassertion
- From: "Thomas Schutt" <Thomas_Schutt@splashtech.com>
- Boot analysis from PCI
- From: Michel.Aubert@itmi.cgs.fr (Michel Aubert)
- Reminder - Upcoming HRPCI meetings
- RE: PPB inability to separate VGA/MONO cycles
- From: "Thomas C. Block" <thomas_block@nine.com>
- Simulating/verifying PCI bidir requirements
- From: kevin.normoyle@Eng.Sun.COM (Kevin Normoyle)
- FW: PPB inability to separate VGA/MONO cycles
- From: "Thomas C. Block" <thomas_block@nine.com>
- Re: Unidentified subject!
- From: "John R Pierce" <pierce@hogranch.com>
- Power sequencing (3.3 V/5 V)
- From: Pavel.Peleska@mch.scn.de
- Unidentified subject!
- From: robertm@marte.cinv.iteso.mx (Roberto Medina)
- Re: bad PCI cycles
- From: khp@dolphinics.no (Kai Harrekilde-Petersen)
- bad PCI cycles
- P1996 HRPCI Minutes from 12/10/96 Meeting
- PCI SIG January Events
- From: Warren Questo <Warren_Questo@ccm.fm.intel.com>
- 5V-3.3V combo connectors
- From: jgarver@ichips.intel.com
- Re: interrupt latency...
- From: "John R Pierce" <pierce@hogranch.com>
- Re: PCI Raw Card
- From: "Johnson, Ralph" <ralphj@bit3.com>
- Re: interrupt latency...
- From: "David O'Shea" <daveo@corollary.com>
- Re: interrupt latency...
- From: Dave New <den@aisinc.com>
- PCI Raw Card
- From: YoelL@vcon.co.il (Yoel lavian)
- interrupt latency...
- From: "Jasper Balraj" <jasper@utopia.hclt.com>
- Subsystem Vendor ID
- From: Rafi Boneh <RAFIB@GILAT.MHS.CompuServe.COM>
- Re: PCI Raw Card
- From: "Thomas Schutt" <Thomas_Schutt@splashtech.com>
- re: What does no EROM look like?
- From: frances_cohen@ptltd.com
- What does no EROM look like?
- From: bkd@auratek.com (Bjoren Davis)
- RE: Burst Write Transfers from PC Host's Perspective
- From: Brian Carlson <bcarlson@dnaent.com>
- Re: Burst Write Transfers from PC Host's Perspective
- From: Dave New <den@aisinc.com>
- Re: Burst Write Transfers from PC Host's Perspective
- From: "John R Pierce" <pierce@hogranch.com>
- Burst Write Transfers from PC Host's Perspective
- From: Brian Carlson <bcarlson@dnaent.com>
- Re: SVGA cards on PCI and store gathering
- From: Noam Halevy <noamh@msil.sps.mot.com>
- Re: SVGA cards on PCI
- From: "Bender, Bernhard" <br@elsa.de>
- Re: SVGA cards on PCI
- From: "John R Pierce" <pierce@hogranch.com>
- Re: SVGA cards on PCI and store gathering
- From: Noam Halevy <noamh@msil.sps.mot.com>
- Re: SVGA cards on PCI
- From: "chefren" <chefren@pi.net>
- Re: SVGA cards on PCI and store gathering
- From: havard@brooktree.com (havard scott)
- Re: SVGA cards on PCI
- From: "John R Pierce" <pierce@hogranch.com>
- Re: SVGA cards on PCI
- From: eric@scn.org (Eric Rehm)
- Re: SVGA cards on PCI and store gathering
- From: Tom Hicks <thicks@fore.com>
- Re: SVGA cards on PCI and store gathering
- From: Noam Halevy <noamh@msil.sps.mot.com>
- Re: SVGA cards on PCI and store gathering
- From: "John R Pierce" <pierce@hogranch.com>
- Re: SVGA cards on PCI
- From: "Thomas Schutt" <Thomas_Schutt@splashtech.com>
- Re: SVGA cards on PCI and store gathering
- From: Noam Halevy <noamh@msil.sps.mot.com>
- Re: SVGA cards on PCI
- From: "John R Pierce" <pierce@hogranch.com>
- SVGA cards on PCI
- From: Noam Halevy <noamh@msil.sps.mot.com>
- Re: Latency Timer value of 0
- From: Tom Hicks <thicks@fore.com>
- Latency Timer value of 0
- From: Joe Cowan <jpc@hpmckee.fc.hp.com>
- Reminder: P1996 Meeting 12/10/96
- Resource Allocation Problem
- From: Timothy Hellman/PicTel <Timothy_Hellman@smtpnotes.pictel.com>
- Re: Some questions
- From: Graeme Gill <graeme@digideas.com.au>
- RE: Some questions
- From: "Kimmery, Clifford (FL51)" <kimmery@space.honeywell.com>
- Re: Some questions
- From: "John R Pierce" <pierce@hogranch.com>
- Re: Some questions
- From: "John R Pierce" <pierce@hogranch.com>
- Resource Allocation Problem
- Re: Some questions
- From: Mark Gonzales <markg@scic.intel.com>
- RE: Some questions
- From: "Kimmery, Clifford (FL51)" <kimmery@space.honeywell.com>
- Re: Some questions
- From: "David O'Shea" <daveo@corollary.com>
- Re: Some questions
- From: "John R Pierce" <pierce@hogranch.com>
- Unused memory bars allowed
- From: "Gardiner C, BSHEPS" <CHARLES.GARDINER@S31.MCH1.x400.sni.de>
- Re: Some questions
- From: Duane Clark <Duane.Clark@jpl.nasa.gov>
- 5V signal pull-up/down VI curve
- From: "Larp Lee" <larp_lee@qualitysemi.com>
- Re: Unused memory bars allowed
- From: frank.story@tempe.vlsi.com
- Target Initial/Subsequential Latency
- From: Braun_Josef#Tel3805 <bj3805@denbgm31m.scnn1.msmgate.m30x.nbg.scn.de>
- Re: Target Initial/Subsequential Latency
- From: Andrew Crosland <crosland@radstone.co.uk>
- Re: Target Initial/Subsequential Latency
- From: larky@anchorchips.com (Steven Larky)
- Unused memory bars allowed
- From: Carsten Bode <cb@Diehl.DE>
- Max PCI clock frequency
- From: Carsten Bode <cb@Diehl.DE>
- FW: Target Initial/Subsequential Latency
- From: "Taylor, Mike" <mike@buntypost.dundee.ncr.com>
- Interleaving Memory Addresses On PCI Boards
- From: davidc@kbd.com.au (David Chung)
- RE: Compact PCI
- From: Noel Poore <np@tadpole.co.uk>
- Re: Some questions
- From: "chefren" <chefren@pi.net>
- Re: Some questions
- From: png@woof.net (Peter N. Glaskowsky)
- Re: Some questions
- From: cary@agora.rdrop.com (David Cary)
- Re: Some questions
- From: "John R Pierce" <pierce@hogranch.com>
- PCI-to-PCI Bridge model
- From: Boaz Ben-nun <boaz@trimedia.scs.philips.com>
- Some questions
- From: robertm@marte.cinv.iteso.mx (Roberto Medina)
- FCode Driver Class will be held on January 13 - 16, 1997
- From: "Gregory R. Hill" <gregh@FirmWorks.COM>
- Re: CPU - PCI cycles
- From: Braun_Josef#Tel3805 <bj3805@denbgm31m.scnn1.msmgate.m30x.nbg.scn.de>
- Re: CPU - PCI cycles
- From: richardm@cd.com (Richard Masoner)
- Re: CPU-PCI cycles
- From: Andreas Heiner <Andreas.Heiner@fr.bosch.de>
- Re: CPU - PCI cycles
- From: "John R Pierce" <pierce@hogranch.com>
- CPU - PCI cycles
- From: Rafi Boneh <RAFIB@GILAT.MHS.CompuServe.COM>
- FW: BIOS and BARs
- From: "Taylor, Mike" <mike@buntypost.dundee.ncr.com>
- Siemens Munich - PCI interface
- From: "chefren" <chefren@pi.net>
- No Subject
- From: Gene Glick <GGLI@dictaphone.com>
- Re: Trouble running in Dual bus boxes under NT
- From: v_chau@emulex.com (Vi Chau)
- Re: BIOS and BARs
- From: "David O'Shea" <daveo@corollary.com>
- PCI short form factor
- From: "Johnson, Ralph" <ralphj@bit3.com>
- PCI BIOS 32 Service and Novell 4.1X, 3.12
- From: David Marcionek <dmarcio@unicore.com>
- Subcription
- From: "Sudhakar" <sudhakar%cdc.znyx.com@netcom.com>
- Hot Swapping With PCI
- From: Phil Cupryk <Phil.Cupryk@Matrox.COM>
- Re: BIOS and BARs
- From: "Bender, Bernhard" <br@elsa.de>
- Re: Trouble running in Dual bus boxes under NT
- From: "Bender, Bernhard" <br@elsa.de>
- BIOS and BARs
- From: ABIVEN Anne <ABIVEN@crf.canon.fr>
- Re: BIOS and BARs
- From: Berg Ingvar <ingvar.berg@team.icl.se> (Tel +46-13-31 7887)
- Detected Parity Error bits on multi-function devices
- From: frank.story@tempe.vlsi.com
- PCI bus power management specification
- From: Warren Questo <Warren_Questo@ccm.fm.intel.com>
- Trouble running in Dual bus boxes under NT
- From: v_chau@emulex.com (Vi Chau)
- Returned mail: User unknown
- From: Mail Delivery Subsystem <MAILER-DAEMON@bilbo2.pic.net>
- Internet problems...
- From: Alan Deikman <alan@znyx.com>
- 64bit PCI Interface chip for adapter?
- From: IDA Tomoyuki <ida@lan.land.fc.nec.co.jp>
- Re: Target Termination Rules
- From: Tom Hicks <thicks@fore.com>
- Re: pci bus test card
- From: Markus Sellmair <Markus.Sellmair@mch.sni.de>
- Re: pci bus test card
- From: "John R Pierce" <pierce@hogranch.com>
- Target Termination Rules
- From: Christian Huter <cmhuter@stud.ee.ethz.ch>
- Re: pci bus test card
- From: rowi@force.de (Robert Wieser)
- pci bus test card
- From: Markus Sellmair <Markus.Sellmair@mch.sni.de>
- I2O Products
- From: Wolfgang Christl <christl.muc@sni.de>
- Real 1GHz digitizer card
- From: rs@bruker.com (Reto Stamm)
- How to complete a transaction caused by
- From: Braun_Josef#Tel3805 <bj3805@denbgm31m.scnn1.msmgate.m30x.nbg.scn.de>
- Virtual Chips (formerly RAVIcad) PCI Core info requested.
- From: danj@austx.tandem.com (Dan Joyce)
- Re: MRM, MRL, MWI question
- From: "Monish Shah" <monish@hpfcmss.fc.hp.com>
- Re: How to complete a transaction caused by
- From: "Monish Shah" <monish@hpfcmss.fc.hp.com>
- MRM, MRL, MWI question
- From: holeman@mpd.tandem.com (Jim Holeman)
- Re: 3.3V Decoupling
- From: ivor@peritek.com (Ivor Bowden)
- FW: 3.3V Decoupling
- From: "Taylor, Mike" <mike@buntypost.dundee.ncr.com>
- Compatibility
- From: rs@bruker.com (Reto Stamm)
- 3.3V Decoupling
- From: Jerry Sabath <sabath@atla3.agfa.com>
- Re: 3.3V Decoupling
- From: "John R Pierce" <pierce@scruznet.com>
- DPMI question
- From: "Rajiv Agrawal" <rajiva@hotmail.com>
- FW: how do we write a single byte in the CSR...
- From: "Taylor, Mike" <mike@buntypost.dundee.ncr.com>
- Re: Compatibility
- From: "John R Pierce" <pierce@scruznet.com>
- Re: trace length
- From: mellitz@eagle.ColumbiaSC.NCR.COM
- how do we write a single byte in the CSR...
- From: "Jasper Balraj" <jasper@utopia.hclt.com>
- RE: how do we write a single byte in the config. registers?
- From: "Taylor, Mike" <mike@buntypost.dundee.ncr.com>
- Re: how do we write a single byte in the config. registers?
- From: "John R Pierce" <pierce@scruznet.com>
- RE: checking for the presence of PCI BIOS...
- From: rdunlap@atlanta.nsc.com (Randy Dunlap)
- RE: checking for the presence of PCI BIOS...
- From: ingvar_berg@x400.icl.co.uk
- trace length
- From: Tobias Stumber <tobias.stumber@fr.bosch.de>
- checking for the presence of PCI BIOS...
- From: "Jasper Balraj" <jasper@utopia.hclt.com>
- FW: how do we write a single byte in the config. registers?
- From: "Taylor, Mike" <mike@buntypost.dundee.ncr.com>
- Re: how do we write a single byte in the config. registers?
- From: se@freebsd.org (Stefan Esser)
- Re: how do we write a single byte in the config. registers?
- From: "John R Pierce" <pierce@scruznet.com>
- Hot Swap
- From: "Stephen J. Forde" <sforde@bbn.com>
- RE: how do we write a single byte in the config. registers?
- From: ingvar_berg@x400.icl.co.uk
- how do we write a single byte in the config. registers?
- From: "Jasper Balraj" <jasper@utopia.hclt.com>
- PCI to PCI Bridge Help
- From: Dave Johnston <djohnsto@mail1.videoserver.com>
- Re: Question: related to System bus bandwidth
- From: "chefren" <chefren@pi.net>
- Re: 3.3V on a 5V bus
- From: "John R Pierce" <pierce@scruznet.com>
- Re: 3.3V on a 5V bus
- From: cary@agora.rdrop.com (David Cary)
- Re: Question: related to System bus bandwidth
- From: gsc@Traveller.COM (GSC)
- Re: Question: related to System bus bandwidth
- From: John R Pierce <pierce@scruznet.com>
- Question: related to System bus bandwidth
- From: subbarao@rd.smos.com (Arumilli Subbarao 12/08/95)
- Re: Non-Host CPU/PCI Bridge
- From: Andrew Crosland <crosland@radstone.co.uk>
- Non-Host CPU/PCI Bridge
- From: Jean-Jacques.Lecler@masi.ibp.fr (Jean-Jacques LECLER)
- Re: HP's proposal for PCI specification modification
- From: Francisco Corella <fcorella@gslxsrv2.rose.hp.com>
- P6 bursting
- From: kguy <kguy@a-d-inc.com>
- Re: PCI market trend info, png's take
- From: Charles Curley ETW <ccurley@dwarf.fc.hp.com>
- RE: non-consistent byte enables
- From: Norman J Rasmussen <Norman_J_Rasmussen@ccm.jf.intel.com>
- Re: PCI market trend info, png's take
- From: Terry Trausch <TTrausch@msmail.radisys.com>
- RE: non-consistent byte enables
- From: Terry Trausch <TTrausch@msmail.radisys.com>
- Re: endian-ness
- From: Adam Barnes <amb@transtech.co.uk>
- Endian-ness
- From: brians@Aureal.com (Brian Sassone)
- Need Comms I/F board
- From: Jeff Brown <sensys2@erols.com>
- PCI market trend info, png's take
- From: png@woof.net (Peter N. Glaskowsky)
- Re: vacation autoreplies and mailling lists...
- From: havard@brooktree.com (havard scott)
- vacation autoreplies and mailling lists...
- From: "John R Pierce" <pierce@scruznet.com>
- Re: Pointer to PCI market trend info
- From: "John R Pierce" <pierce@scruznet.com>
- Pointer to PCI market trend info
- From: Leo Salazar <leo@shawn.com>
- non-consistent byte enables
- From: Suzie Gemignani <Suzie.Gemignani@tsc.tdk.com>
- Re: PCI Workshop in Tel Aviv
- From: Leonid Smolyansky <leonid@msil.sps.mot.com>
- PCI Workshop in Tel Aviv
- From: leon@Orbotech.Co.IL (Leon Koll)
- November 14 Meeting of HRPCI (P1996)
- Re: 3.3V on a 5V bus
- From: Andy Ingraham <ingraham@wrksys.ENET.dec.com>
- Hight between connector and card ?
- From: Horie Akira <horie@os.nasu.toshiba.co.jp>
- 3.3V on a 5V bus
- From: "Jens-Peter K. Jensen" <dantecmt/adm/432jpj@dantecmt.dk>
- JMS on CompuServe (Nov 08, 1996) *POSSIBLE SPOILERS*
- From: Brent Barrett <bbarrett@speedlink.com>
- Burn-in PCI Host
- From: Corey Anderson <Corey@RNS.COM>
- RE: Please explain rule 1 of Target Term
- From: Braun_Josef#Tel3805 <bj3805@denbgm31m.scnn1.msmgate.m30x.nbg.scn.de>
- Re: Unidentified subject!
- From: ivor@peritek.com (Ivor Bowden)
- Re: PCI Expansion Box
- From: "Augustine, Eric" <erica@bit3.com>
- pci expansion box
- From: Bruno Fierens <BF@bono.barco.com>
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