Mail Index

• Thread Index

• PCI Interrupts
  • From: henrylau@cts.com (Henry Lau)
• RE: Power Managment
  • From: ingvar_berg@x400.icl.co.uk
• PCI SIG Arbiter newsletter?
  • From: Matt Kaufman <mek@sco.COM>
• USB Enabled Motherboards
  • From: GLENN STERN <GLENN.STERN@mail.mei.com>
• ISA Retainer bracket info requested for PCI add-on
  • From: GANESANV@american.megatrends.com (GANESANV)
• Arbitration question (GNT#->FRAME# latency)
  • From: Tom Hicks <thicks@fore.com>
• RE: Power Managment
  • From: Eric Rehm <eric@equator.com>
• Power Managment
  • From: Eric Rehm <eric@equator.com>
• PCI Deadlock Handling
  • From: "paul (p.n.) ramsden" <ramsden@nortel.ca>
• Intel Triton 430FX chipset and bus mastering PCI cards
  • From: Adam Barnes <amb@transtech.co.uk>
• Re: To snoop or not to snoop...
  • From: "John R Pierce" <pierce@scruznet.com>
• RE: Linear address mapping
  • From: Jim Ulrich <jimu@pathlight.com>
• Specs now available for PLX’s PCI 9050 target chip
  • From: Mike Salameh <mike_salameh@plxtech.com>
• PLX's NEW PCI TARGET CHIP
  • From: Mike Salameh <mike_salameh@plxtech.com>
• SHARCs in PCI and VME
  • From: "Ebert, Thomas" <te@wiese.de>
• Linear address mapping
  • From: Tobias Stumber <tobias.stumber@fr.bosch.de>
• To snoop or not to snoop...
  • From: Dave New <den@aisinc.com>
• Re: VGA Palette snoopining
  • From: "John R Pierce" <pierce@scruznet.com>
• Re: VGA Palette snoopining
  • From: Devendra K Tripathi <tripathi@Synopsys.COM>
• VGA Palette snoopining
  • From: mo@rendition.com (Mohammed Sriti)
• re: PCI COMPLIANCE
  • From: "FuturePlus: Barbara A." <71035.3052@compuserve.com>
• CardBus Power Management
  • From: Niels_Johansen@olicom.dk
• Fast Back to Back transfers
  • From: re <roneis@lightspeed.net>
• Re: Right-Angle PMC
  • From: holeman@lumeria.mpd.tandem.com (Jim Holeman)
• PCI DRAM Controller
  • From: Peter Ma <ma@idacom.hp.com>
• Re: PCI Target Addressing and AD[1:0]
  • From: Devendra K Tripathi <tripathi@Synopsys.COM>
• Right-Angle PMC
  • From: "Frank Seeker-P27089" <Frank_Seeker-P27089@email.mot.com>
• Chaining of PCMCIA Cardbus controllers
  • From: Braun_Josef#Tel3805 <bj3805@denbgm31m.scnn1.msmgate.m30x.nbg.scn.de>
• PCI Target Addressing and AD[1:0]
  • From: pci-sig-request@znyx.com
• HP announces new PCI Analyzer & Exerciser
  • From: Thomas Dippon <thomasd@hpbidrd.bbn.hp.com>
• Interest Survey: Bracket to expand to full ISA Size
  • From: "Raymond J. Clark" <clark@scan.mc.xerox.com>
• PCI address and ad[1:0]
  • From: \dart.znyx.com@RNS.COM (Larry Gerald)
• Cards that can master in 64-bit space??
  • From: John Wisneski <johnw@kiowa.fc.hp.com>
• multi-board devices?
  • From: Matt Kaufman <mek@sco.COM>
• Cycles with no BEs
  • From: Paul Garnett <Paul.Garnett@UK.Sun.COM>
• Re: PCI Hot Swap
  • From: Paul Walker <paul@walker.demon.co.uk>
• 5 PCI slots?
  • From: "Randy Banton" <randy_banton@mc.com>
• How does 3.3V 5V PCI buffers are toggeled.
  • From: "Yehuda D. Yizraeli" <yehuda@chipx.co.il>
• Re: How does 3.3V 5V PCI buffers are toggeled.
  • From: "Monish Shah" <monish@mcsy2.fc.hp.com>
• Re: How does 3.3V 5V PCI buffers are toggeled.
  • From: Andy Ingraham 17-Sep-1996 1047 <ingraham@wrksys.ENET.dec.com>
• PCI Hot Swap
  • From: Phil Cupryk <Phil.Cupryk@Matrox.COM>
• Host Bridge: Read Retry
  • From: Pavel.Peleska@mch.scn.de
• Large Motherboard.
  • From: "Medley, Jerry" <jerrym@bit3.com>
• PCI Compliance
  • From: Reza Vahedi <reza@cognex.com>
• Add-in DSP Cards
  • From: olsonc@master.tds-az.lmco.com (Chris Olson)
• Re: Burst Accesses from Host to Target?
  • From: "John R Pierce" <pierce@scruznet.com>
• Burst Accesses from Host to Target?
  • From: Richard Burk <RBURK@datx.com>
• Re: question on PCI spec regarding Cacheline Register
  • From: Frank Helms <frank.helms@amd.com>
• PMC - 5V or 3.3V?
  • From: Simon Cameron <simonc@Vsl.Com.Au>
• question on PCI spec regarding Cacheline Register
  • From: larry@mercury.RNS.COM (Larry Gerald)
• Comments on PCI power management.
  • From: Niels_Johansen@olicom.dk
• Re: Large Motherboard.
  • From: richardm@cd.com (Richard Masoner)
• RE: DMA channels with PCI devices
  • From: Craig Mathewson <craig@sederta.com>
• Solutions for PCs needing Secondary PCI
  • From: Barry McGugan <barry_mcgugan@gilbarco.com>
• Re: DMA channels with PCI devices
  • From: Hans Berglund <hb@spacetec.no>
• Re: Large Motherboard.
  • From: "John M. Keefe, Jr." <keefe@magma.COM>
• Re: PCI Memory Devices
  • From: png@woof.net (Peter N. Glaskowsky)
• Re: DMA channels with PCI devices
  • From: Stephen Williams <steve@icarus.com>
• DMA channels with PCI devices
  • From: Craig Mathewson <craig@sederta.com>
• Mechanical error
  • From: Rafi Boneh <RAFIB@GILAT.MHS.CompuServe.COM>
• Re: PCI Memory Devices
  • From: Eric Ryherd <eric@vautomation.com>
• Clarifications on 3.3 volt PCI I/Os
  • From: "Raymond Gaita" <optmagic@ix.netcom.com>
• Re: Large Motherboard.
  • From: Vandana Lokeshwar <vanlok@aztech.com.sg>
• PCI to PCI bridge
  • From: RAMIB@nulan.co.il
• Large Motherboard.
  • From: Rafi Boneh <RAFIB@GILAT.MHS.CompuServe.COM>
• Re: PCI Memory Devices
  • From: "chefren" <chefren@pi.net>
• Engineering Change Request (ECR) for IRQ Routing
  • From: "David O'Shea" <daveo@corollary.com>
• Re: PCI Memory Devices
  • From: Eric Ryherd <eric@vautomation.com>
• RE: PCI DMA Controller
  • From: tedlu@ix.netcom.com
• PCI to memory bandwidth
  • From: Bruce Pirger <pirger@iras3.tn.cornell.edu>
• base addresses
  • From: lofgrenj@real3d.com
• PCI DMA Controller
  • From: "Frank Moore" <fmoore@msai.mea.com>
• Hot Plug Workgroup
  • From: Warren Questo <Warren_Questo@ccm.fm.intel.com>
• Re: PCI Memory Devices
  • From: Steven E Rice <stever@mdhost.cse.tek.com>
• Re: Pci to Pci transfers
  • From: "Monish Shah" <monish@mcsy2.fc.hp.com>
• RE: Pci to Pci transfers
  • From: Jim Ulrich <jimu@pathlight.com>
• Pci to Pci transfers
  • From: hsu@ocegr.fr (Herve Suquet)
• Re: Expansion card debugging
  • From: cary@agora.rdrop.com (David Cary)
• Re: PCI Memory Devices
  • From: "John R Pierce" <pierce@scruznet.com>
• Re: Support for LOCK#
  • From: Andrew Crosland <crosland@radstone.co.uk>
• PCI Memory Devices
  • From: dpagano@hpmail2.fwrdc.rtsg.mot.com (Daniel Pagano)
• AGP Master Model
  • From: Frank Helms <frank.helms@amd.com>
• Re: Support for LOCK#
  • From: "Monish Shah" <monish@mcsy2.fc.hp.com>
• Support for LOCK#
  • From: "Belvin Stephen E" <belvin_stephen_e@smtp2.space.honeywell.com>
• Implementation of PCI interface
  • From: Simon Cameron <simonc@Vsl.Com.Au>
• Re: NATOMA 440FX PCI CHIPSET - WINDOWS NT AND AMCC S5933
  • From: Frank Hady <Frank_Hady@ccm.jf.intel.com>
• re: Only Some BARs initialized?
  • From: drj@bangate.compaq.com
• Only Some BARs initialized?
  • From: rwalter@auspex.com (Richard Walter)
• NATOMA 440FX PCI CHIPSET - WINDOWS NT AND AMCC S5933
  • From: LEROUXJ@tmmrdf1.rennes.tcetbs1.thomson.fr
• Re: PCI signals trace length
  • From: Andy Ingraham <ingraham@wrksys.ENET.dec.com>
• Re: IEEE P1996 Meeting - High Reliability PCI Bus [Sept 26] (fwd)
  • From: Jochen Roth <jochen@znyx.com>
• IEEE P1996 Meeting - High Reliability PCI Bus [Sept 26] (fwd)
  • From: alan@znyx.com (Alan Deikman)
• Correction
  • From: Chris Malcheski <71232.360@CompuServe.COM>
• PCI signals trace length
  • From: mo@rendition.com (Mohammed Sriti)
• Re: MWI bus cycles
  • From: "Shivakumar S. Chonnad" <shiv@Synopsys.COM>
• RE: PCI Class Codes
  • From: "Summit, Ed" <Ed_Summit@cissc.canon.com>
• MWI bus cycles
  • From: Don Fry <donf@sequent.com>
• SHARCs in PCI or VME
  • From: thebert@tom.on-luebeck.de (Thomas Ebert)
• Re: Config area (yet again)
  • From: jww@anchor.eng.hou.compaq.com (Jeff Wolford)
• Re: A BAR of 0 = disabled.
  • From: Charles Curley ETW <ccurley@dwarf.fc.hp.com>
• I960RP and BAR size
  • From: Jim Ulrich <jimu@pathlight.com>
• RE: A BAR of 0 = disabled.
  • From: Devendra K Tripathi <tripathi@Synopsys.COM>
• RE: A BAR of 0 = disabled
  • From: Daniele Beccari <daniele@petrus.grenoble.hp.com>
• RE: A BAR of 0 = disabled.
  • From: "Belvin Stephen E" <belvin_stephen_e@smtp2.space.honeywell.com>
• Re: A BAR of 0 = disabled.
  • From: goudreau@dg-rtp.dg.com (Bob Goudreau)
• DEC Alpha and PCI bursts
  • From: Mitch Norcross <mitch@sunsvr.Pixera.com>
• A BAR of 0 = disabled.
  • From: rwalter@auspex.com (Richard Walter)
• Re: PC Com ports on PCI... Problems ???
  • From: "John R Pierce" <pierce@scruznet.com>
• AMCC's S5933 Pass-thru interface
  • From: DaMiAn <gdma@zorba.inesc.pt>
• Re: Expansion card debugging
  • From: Vandana Lokeshwar <vanlok@aztech.com.sg>
• RE: Burst reads required?
  • From: Simon Cameron <simonc@Vsl.Com.Au>
• Re: PC Com ports on PCI... Problems ???
  • From: Michael.Bender@Eng.Sun.COM (Michael Bender)
• Re: PC Com ports on PCI... Problems ???
  • From: Tom Warren <tom.warren@tempe.vlsi.com>
• SMT TAP connector..
  • From: "Don Abernathey" <dla@pyramid.com>
• PC Com ports on PCI... Problems ???
  • From: mike.hollenbeck@TSDMS1.SSI1.COM (mike hollenbeck)
• Re: BIOS behavior on BIOS and memory space enable bit
  • From: wen-king@myri.com (Wen-King Su)
• Re: BIOS behavior on BIOS and memory space enable bit
  • From: Tom Warren <tom.warren@tempe.vlsi.com>
• VMETRO PDRIVE
  • From: Carey Sasser <sasser@hp4.nmg.sms.siemens.com>
• Multi-function Devices
  • From: GORD@atitech.ca (Gord Caruk)
• BIOS behavior on BIOS and memory space enable bit
  • From: wen-king@myri.com (Wen-King Su)
• Config area (yet again)
  • From: Chris Malcheski <71232.360@CompuServe.COM>
• RE: Pci to Pci transfers
  • From: "jim busse" <jim_busse@email.award.com>
• Expansion card debugging
  • From: Carey Sasser <sasser@hp4.nmg.sms.siemens.com>
• RE: Burst reads required?
  • From: Alexei Predtechenski <Alexei.Predechenski@amd.com>
• Re: Pci to Pci transfers
  • From: Ali Najafi <alinajafi@aztech.com.sg>
• Pci to Pci transfers
  • From: hsu@ocegr.fr (Herve Suquet)
• fwd: RE: PCI Mobile Design Guide
  • From: Bruce Young <Bruce_Young@ccm.jf.intel.com>
• fwd: RE: PCI Mobile Design Guide
  • From: Joseph Tung <a0384591@dtes13.itg.ti.com>
• New PCI SIG web page
  • From: rbaekvtm@teleport.com (RICHARD BAEK)
• archive?
  • From: Mitch Norcross <mitch@sunsvr.Pixera.com>
• RE: PCI interrupt request and PC platform
  • From: ingvar_berg@x400.icl.co.uk
• PCI interrupt request and PC platform
  • From: Ali Najafi <alinajafi@aztech.com.sg>
• RE: PCI to PCI Bridge with 2 independent clocks
  • From: "To H. Lam" <to@vcubed.com>
• Re: PCI I/O vs Memory space
  • From: kimmel@dg-rtp.dg.com (Jeff Kimmel)
• Re: PCI I/O vs Memory space
  • From: jww@anchor.eng.hou.compaq.com (Jeff Wolford)
• Re: PCI capabilities
  • From: Frank Helms <frank.helms@amd.com>
• Question on PLX PCI interface device
  • From: henrylau@cts.com (Henry Lau)
• Re: PMC
  • From: holeman@lumeria.mpd.tandem.com (Jim Holeman)
• PCI capabilities
  • From: lester@ixtapa.eng.hou.compaq.com (Robert Lester)
• Re: FW: Delayed Xaction and LOCK#
  • From: ghickey@cyclone.com (Geoff Hickey)
• Re: Using LOCK# to prevent deadlock
  • From: "Monish Shah" <monish@mcsy2.fc.hp.com>
• re: BIOS Latency
  • From: frances_cohen@ptltd.com
• Burst reads required?
  • From: weathert@arl.wustl.edu (William N. Eatherton)
• re: TNT and extended memory under Win95
  • From: Adam Barnes <amb@transtech.co.uk>
• re: Accessing memory with TNT
  • From: henrylau@cts.com (Henry Lau)
• Re: PCI Audio
  • From: Dave Haynie <dave.haynie@scala.com>
• PMC
  • From: Paul Wilson <wilsonp@emc.com>
• Re: FW: Delayed Xaction and LOCK#
  • From: "Monish Shah" <monish@mcsy2.fc.hp.com>
• Re: PCI Single Card which has the PCI LAN and Modem or ISDN (Multi function PCI board)
  • From: "John R Pierce" <pierce@scruznet.com>
• Unidentified subject!
  • From: frank.story@TEMPE.VLSI.COM
• Re: FW: Delayed Xaction and LOCK#
  • From: frank.story@tempe.vlsi.com
• PCI Compliance Workshops
  • From: Warren Questo <Warren_Questo@ccm.fm.intel.com>
• re: Accessing memory with TNT
  • From: Adam Barnes <amb@transtech.co.uk>
• PCI Single Card which has the PCI LAN and Modem or ISDN (Multi function PCI board)
  • From: ksuzukih <haruji.suzuki@tokyo.ssi1.com>
• Re: PCI Audio
  • From: "John R Pierce" <pierce@scruznet.com>
• PCI Audio
  • From: Suguna R <suguna@aztech.com.sg>
• Re: FW: Delayed Xaction and LOCK#
  • From: Alan Deikman <alan@znyx.com>
• Re: FW: Delayed Xaction and LOCK#
  • From: <d_schneider@emulex.com>
• Re: FW: Delayed Xaction and LOCK#
  • From: "Monish Shah" <monish@mcsy2.fc.hp.com>
• Accessing memory with TNT
  • From: henrylau@cts.com (Henry Lau)
• Re: FW: Delayed Xaction and LOCK#
  • From: Mark Gonzales <markg@scic.intel.com>
• FW: Delayed Xaction and LOCK#
  • From: <d_schneider@emulex.com>
• Host bridge latency on ALPHA Server
  • From: fmj@pe.dk (Finn Martin Johansen)
• Host bridge latency on ALPHA Server
  • From: fmj@pe.dk (Finn Martin Johansen)
• BIOS Latency
  • From: YoelL@vcon-nt.vcon.co.il (Yoel lavian)
• Re: Delayed Xaction and LOCK#
  • From: "Monish Shah" <monish@mcsy2.fc.hp.com>
• RE: PCI to PCI Bridge with 2 independant clocks
  • From: Jim Ulrich <jimu@pathlight.com>
• Re: PCI I/O space on DEC Alpha machines
  • From: richardm@cd.com (Richard Masoner)
• AMD is Hiring for X86 Chipset Design and Verification
  • From: Frank Helms <frank.helms@amd.com>
• Re: PCI live lock
  • From: Keith Chan <kychan@aver.com>
• PCI I/O space on DEC Alpha machines
  • From: Mitch Norcross <mitch@sunsvr.Pixera.com>
• REQ64# and ACK64# on passive backplane
  • From: Jason Trizna <jbt@mclean.sparta.com>
• Re: Delayed Xaction and LOCK#
  • From: rwalter@auspex.com (Richard Walter)
• Re: Delayed Xaction and LOCK#
  • From: Devendra K Tripathi <tripathi@Synopsys.COM>
• Re: Delayed Xaction and LOCK#
  • From: Devendra K Tripathi <tripathi@Synopsys.COM>
• Re: Delayed Xaction and LOCK#
  • From: frank.story@tempe.vlsi.com
• Re: Delayed Xaction and LOCK#
  • From: "Monish Shah" <monish@mcsy2.fc.hp.com>
• Delayed Xaction and LOCK#
  • From: Devendra K Tripathi <tripathi@Synopsys.COM>
• Re: cache line size
  • From: Devendra K Tripathi <tripathi@Synopsys.COM>
• Re: cache line size
  • From: "John & Ruth Pierce" <pierce@scruznet.com>
• PCI serial download
  • From: kguy <kguy@a-d-inc.com>
• RE: PCI to PCI Bridge with 2 independant clocks
  • From: rwalter@auspex.com (Richard Walter)
• RE: PCI to PCI Bridge with 2 independant clocks
  • From: johnp@iia.com
• cache line size
  • From: Devendra K Tripathi <tripathi@Synopsys.COM>
• PMC busmode pins
  • From: ecordero@VNET.IBM.COM
• RE: PCI to PCI Bridge with 2 independant clocks
  • From: Jim Ulrich <jimu@pathlight.com>
• PCI to PCI Bridge with 2 independant clocks
  • From: maubert@itmi.cgs.fr (Michel Aubert)
• Using connectors while on an extender
  • From: jdahlin@precisionimages.com
• Re: PCI I/O Space Consumption Limitation
  • From: "Monish Shah" <monish@mcsy2.fc.hp.com>
• RE: PCI I/O Space Consumption Limitation
  • From: "Belvin Stephen E" <belvin_stephen_e@smtp2.space.honeywell.com>
• Re: Running PCI cards at slow clock speeds
  • From: holeman@devnull.mpd.tandem.com (Jim Holeman)
• Re: Running PCI cards at slow clock speeds
  • From: johnp@iia.com
• CardBus/Yenta-aware PC BIOSes?
  • From: Michael.Bender@Eng.Sun.COM (Michael Bender)
• Delayed (initial) IRDY
  • From: robert@lsi.melco.co.jp (streitenberger robert)
• Re: FW: Re[2]: PCI I/O Space Consumption Limitation
  • From: Mark Gonzales <markg@scic.intel.com>
• Re: PCI I/O Space Consumption Limitation
  • From: "David O'Shea" <daveo@corollary.com>
• Re: Delayed (initial) IRDY
  • From: Tom Keaveny <tak@core.rose.hp.com>
• asymmetrical target and master interfaces
  • From: v_chau@emulex.com (Vi Chau)
• PCI serial download
  • From: kguy <kguy@a-d-inc.com>
• Running PCI cards at slow clock speeds
  • From: "Witalka, Jerome J RV" <jjw1@PO9.RV.unisys.com>