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- access PCI memory from DOS
- From: JohanHZ@Sycron-IT.com
- Re: access PCI memory from DOS
- From: Ivor Bowden <ivor@peritek.com>
- Re: access PCI memory from DOS
- From: lecos@samsung.co.kr
- RE: access PCI memory from DOS, or linux?
- From: Gord Wait <Gord_Wait@spectrumsignal.com>
- Re: access PCI memory from DOS, or linux?
- From: André David <Andre.David@cern.ch>
- IDE bridge chips, address decoding and byte enables
- From: r55017@email.sps.mot.com (Ryan Mcdaniel)
- Using Multiple BAR's
- From: "Bearzi, Anthony" <abearzi@harris.com>
- RE: Using Multiple BAR's
- From: "Bill Peet" <peet@rtviz.com>
- Re: Using Multiple BAR's
- From: "Weng Tianxiang" <WTX@umem.com>
- Re: Using Multiple BAR's
- From: fmnemeth@rockwellcollins.com
- Re: Using Multiple BAR's
- From: Drew Eckhardt <drew@PoohSticks.ORG>
- RE: RE: Using Multiple BAR's
- From: Lame Brooks-G14738 <Brooks_Lame-G14738@email.mot.com>
- RE: Using Multiple BAR's
- From: "Austin Franklin" <darkroom@ix.netcom.com>
- Re: Using Multiple BAR's
- From: Ivor Bowden <ivor@peritek.com>
- FIFO in PCI memory space
- RE: FIFO in PCI memory space
- From: Sanjay Cartic <scartic@ixiacom.com>
- RE: FIFO in PCI memory space
- From: Richard Walter <rwalter@brocade.com>
- Arbitration Code example
- From: James Murray <jmurray@triscend.com>
- State of Arbiter GNT during PCI Reset
- From: James Murray <jmurray@triscend.com>
- AD_OE timing
- From: "Weng Tianxiang" <WTX@umem.com>
- Re: AD_OE timing
- From: James Murray <jmurray@triscend.com>
- RE: AD_OE timing
- From: Daniel Weaver <dan.weaver@znyx.com>
- Re: AD_OE timing
- From: "Khan Kibria" <kkibria@iss-us.com>
- Re: AD_OE timing
- From: Manfred Kuhland <man@atlantek.com.au>
- IO space devices
- From: r55017@email.sps.mot.com (Ryan Mcdaniel)
- Re: IO space devices
- From: Dimiter Popoff <tgi_earth@yahoo.com>
- Re: IO space devices
- From: "Marco Serafini - QR s.r.l" <r&d@qrverona.it>
- Re: IO space devices
- From: "Kevin Sharpe" <kevin.sharpe@btinternet.com>
- RE: IO space devices
- From: "Austin Franklin" <darkroom@ix.netcom.com>
- RE: IO space devices
- From: Dave Chalfant <Dave_Chalfant@phoenix.com>
- pci clock frequency
- From: "Yao Zehui" <ydtcn@21cn.com>
- How to access the pci configuration space?
- From: =?gb2312?B?zfXo6w==?= <wanghua@omc.pim.tsinghua.edu.cn>
- RE: pci clock frequency
- From: "Ingraham, Andrew" <Andrew.Ingraham@compaq.com>
- Command Register IO and Mem Enable Bit
- From: Bert Marston <bert@quadic.com>
- PCI to PCI bridges
- From: "Andrew Krenz" <a.krenz@aristoslogic.com>
- Re: PCI to PCI bridges
- From: "Scott C. Karlin" <scott@CS.Princeton.EDU>
- Fwd: How to access the pci configuration space?
- From: Sagit Kaniel <sagit@jungo.com>
- Re: How to access the pci configuration space?
- From: André David <Andre.David@cern.ch>
- what is master retry timer?
- From: Sanjay Cartic <scartic@ixiacom.com>
- remove
- From: m.lagier@saunierduval.fr
- remove
- From: Fabrice Gens <gens@med.univ-tours.fr>
- Remove
- From: "Shruthi S" <shruthi.raghavan@wipro.com>
- RE: remove
- From: Dustin_Brimberry@Dell.com
- remove
- From: Manish Gilani <manish.gilani@dcmtech.co.in>
- remove
- From: Shizuka Oda <shizuka@xilinx.com>
- remove
- From: Hung Hingtung <tunghung@citicpacific.com>
- remove
- How do I read the IRQ Routing Table with Assembler?
- From: Siegfried Zeh <sizeit00@fht-esslingen.de>
- Re: How do I read the IRQ Routing Table with Assembler?
- From: Bob Smith <bsmith@sudleyplace.com>
- PCI-Local-Bus-Switch Chip Manufacturer
- secofi
- From: "Adrian Martinez"<amartinez@lattice.com.mx>
- remove
- From: Fabrice Gens <gens@med.univ-tours.fr>
- PCI bus monitor/cycle generator
- From: James Murray <jmurray@triscend.com>
- ¸gŔٞdzř§i B88012029
- From: "Kris"<ecpkp@pchome.com.tw>
- looking for pci computers in VITA-32 PMC format
- From: Angel Guirao Elias <angel.guirao.elias@cern.ch>
- July 27th PCI SIG membership meeting?
- From: "Snyder, Cary D. (Cahners)" <cds@mdr.cahners.com>
- burst length
- From: "Marco Serafini - QR s.r.l" <r&d@qrverona.it>
- Archive
- From: wahab@karlnet.com (Mamdouh Wahab)
- RE: burst length
- From: "Hofmans, Kim" <kim.hofmans@barco.com>
- Master REQ# not receiving GNT#
- From: "Daniel DeConinck" <daniel.deconinck@sympatico.ca>
- MASTER GNT# not being issued in response to REQ#
- From: "Daniel DeConinck" <daniel.deconinck@sympatico.ca>
- RE: MASTER GNT# not being issued in response to REQ#
- From: "Hofmans, Kim" <kim.hofmans@barco.com>
- BOARD2
- From: "terry"<jatiq-fhq@21cn.com>
- Question about special cycle parity error
- From: Yanzhe Liu <liu@gdatech.com>
- 21154
- From: "21cn" <ydtcn@21cn.com>
- Re: Question about special cycle parity error
- From: "Weng Tianxiang" <WTX@umem.com>
- Re: 21154
- From: Neal Palmer <neal@dinigroup.com>
- IRQ and 21554.
- From: Christophe.LINDHEIMER@fr.thalesgroup.com
- PCI Retry
- From: r55017@email.sps.mot.com (Ryan Mcdaniel)
- Re: PCI Retry
- From: Amit Shah <ashah10@agere.com>
- Unidentified subject!
- From: GAYATHRI PRABHU <gayathri@crlbel.ernet.in>
- PMC clearances RE: Unidentified subject!
- From: Lame Brooks-G14738 <Brooks_Lame-G14738@email.mot.com>
- PCI Compliance Certificate by PCISIG?
- From: "Reichenbaecher, Olaf" <olaf.reichenbaecher@sci-worx.com>
- Device Select Timing
- From: Siegfried Zeh <sizeit00@fht-esslingen.de>
- RE: Device Select Timing
- From: André David <Andre.David@cern.ch>
- RE: Device Select Timing
- From: "Fockler, Joe" <jfockler@chipdata.com>
- RE: Device Select Timing
- From: "Taylor, Mike" <mike@exchange.SCOTLAND.NCR.com>
- Test Mail
- From: Chandrasekar Srinivasan <chandrasekar.s@dcmtech.co.in>
- INT Lines vs IRQs
- From: Chandrasekar Srinivasan <chandrasekar.s@dcmtech.co.in>
- Re: INT Lines vs IRQs
- From: Drew Eckhardt <drew@PoohSticks.ORG>
- Low Profile PCI
- From: "Taylor, Mike" <mike@exchange.SCOTLAND.NCR.com>
- PCI Signal clamping
- From: Mark van Nobelen <Mark.van.Nobelen@chess.nl>
- Re: PCI Signal clamping
- Diodes to Vi/o? RE: PCI Signal clamping
- From: Lame Brooks-G14738 <Brooks_Lame-G14738@email.mot.com>
- Maximum Outstanding Split Transactions in PCI-X Configuration Control and Status Registers
- From: "Srividya Viswanathan" <srividya.viswanathan@idt.com>
- FW: Maximum Outstanding Split Transactions in PCI-X Configuration Control and Status Registers
- From: "Srividya Viswanathan" <srividya.viswanathan@idt.com>
- Re: Maximum Outstanding Split Transactions in PCI-X Configuration Controland Status Registers
- From: "Richard Iachetta" <iachetta@us.ibm.com>
- Re: FW: Maximum Outstanding Split Transactions in PCI-X Configuration Control and Status Registers
- From: Amit Shah <ashah10@agere.com>
- Re: PCI Signal clamping
- From: Neal Palmer <neal@dinigroup.com>
- RE: PCI Signal clamping
- From: "Bernhard Andretzky" <andretzky@quicklogic.com>
- SSRAM question (off topic)
- From: "John W. Perry" <jperry@dinigroup.com>
- pci interrupt acknowledge cycle
- From: "BANESHWAR M SHANBHAG" <baneshwar.s@lycos.com>
- RE: pci interrupt acknowledge cycle
- From: "Austin Franklin" <darkroom@ix.netcom.com>
- Arbitration/Ordering of Intel Chipset
- From: "Hyun-Wook Jin" <hwjin@os.korea.ac.kr>
- irdy on read
- From: Kevin Normoyle <Kevin.Normoyle@Sun.COM>
- Need device to assert latencies on bus
- From: allan.boerner@conexant.com
- memory prefetchable
- From: "Marco Serafini - QR s.r.l" <r&d@qrverona.it>
- Fwd: Need device to assert latencies on bus
- From: Mike Dini <mdini@dinigroup.com>
- Re: memory prefetchable
- From: Carter Buck <CBuck@PLXTech.com>
- RE: memory prefetchable
- From: "Naert, Hans" <hans.naert@barco.com>
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