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- Re: one more baby step and I an done
- From: "Marco Serafini - QR s.r.l" <r&d@qrverona.it>
- RE: Dual PCI System
- From: "SHEU,PHILIP (HP-Cupertino,ex3)" <psheu@hp.com>
- Re: Dual PCI System
- From: wamnet <wamnet@gte.net>
- Dual PCI System
- From: "Olson, Chris E" <chris.e.olson@lmco.com>
- RE: PCI-X on PMC
- From: Lame Brooks-G14738 <Brooks_Lame-G14738@email.mot.com>
- RE: PMC Spec - Characteristic Impedance Numbers?
- From: Gord Wait <Gord_Wait@spectrumsignal.com>
- RE: PCI bridge I/O space
- From: Lame Brooks-G14738 <Brooks_Lame-G14738@email.mot.com>
- RE: PMC Spec - Characteristic Impedance Numbers?
- From: Lame Brooks-G14738 <Brooks_Lame-G14738@email.mot.com>
- RE: PCI bridge I/O space
- From: Richard Walter <rwalter@brocade.com>
- PCI bridge I/O space
- From: Kit Richards <kit@nso.edu>
- one more baby step and I an done
- From: "Daniel DeConinck" <daniel.deconinck@sympatico.ca>
- PCI-X on PMC
- From: Paul Weber <pweber@sbs.com>
- RE: PMC Spec - Characteristic Impedance Numbers?
- From: "Ingraham, Andrew" <Andrew.Ingraham@compaq.com>
- PMC Spec - Characteristic Impedance Numbers?
- From: Gord Wait <Gord_Wait@spectrumsignal.com>
- RE: Re: Re: access PCI memory from DOS
- From: darkroom@ix.netcom.com
- Re: Re: access PCI memory from DOS
- From: lecos@samsung.co.kr
- Load Tuning of Non Bridge functions
- From: "Kashif Ghafoor" <kasheeg@hotmail.com>
- removal
- From: Jennet Shi <zh_shi@yahoo.com>
- Re: Yet another form factor?
- From: wamnet <wamnet@gte.net>
- RE: Yet another form factor?
- From: "SHEU,PHILIP (HP-Cupertino,ex3)" <psheu@hp.com>
- RE: Yet another form factor?
- From: "SHEU,PHILIP (HP-Cupertino,ex3)" <psheu@hp.com>
- pci-x address order
- From: Uttam Aggarwal <uttam.aggarwal@dcmtech.co.in>
- Yet another form factor?
- From: "Monish Shah" <monish.shah@indranetworks.com>
- Re: Resolving ISA card IRQ interference with PCI INTA# to IRQ assignment
- From: Carter Buck <CBuck@PLXTech.com>
- Re: Resolving ISA card IRQ interference with PCI INTA# to IRQ assignment
- From: Neal Palmer <neal@dinigroup.com>
- RE: PCIX Maximum Load Support
- From: "Ingraham, Andrew" <Andrew.Ingraham@compaq.com>
- Fwd: Re: RE: Resolving ISA card IRQ interference with PCI INTA# to IRQ assignment
- From: Mike Jadon <mikej@umem.com>
- Resolving ISA card IRQ interference with PCI INTA# to IRQ assignment
- From: Mike Jadon <mikej@umem.com>
- PCIX Maximum Load Support
- From: "Asmelash, Abel" <Abel.Asmelash@compaq.com>
- RE: PCI with Bios in Embedded system
- From: Lame Brooks-G14738 <Brooks_Lame-G14738@email.mot.com>
- PCI with Bios in Embedded system
- From: Tom Then <tthen@osi.varianinc.com>
- Re: Memory Allocation !!
- From: "Peter Marek" <peter.marek@marekmicro.de>
- RE: Memory Allocation !!
- From: Sanjay Cartic <scartic@ixiacom.com>
- RE: Memory Allocation !!
- From: Sanjay Cartic <scartic@ixiacom.com>
- Re: Memory Allocation !!
- From: André David <Andre.David@cern.ch>
- Memory Allocation !!
- From: Amit Shah <ashah10@agere.com>
- Problems in configuration
- From: "VENKATESHWARLU V" <vv@myw.ltindia.com>
- What is a PCI 'ping pong' cycle ?
- From: Ramesh Sathianathan <ramesh@0-in.com>
- Re: 4k memory block size
- From: "Peter Marek" <peter.marek@marekmicro.de>
- RE: Compact PCI hotswap
- From: Lame Brooks-G14738 <Brooks_Lame-G14738@email.mot.com>
- 4k memory block size
- From: Ben Yurick <byurick@keithley.com>
- Compact PCI hotswap
- From: Sivasubramanian Prasanna <prasanna_cit97@yahoo.com>
- Re: Fwd: need help writing device driver for own made PCI card
- From: Roy Tannenbaum <roy@jungo.com>
- need help writing device driver for own made PCI card
- From: JohanHZ@Sycron-IT.com
- Re: To the folks looking for stradle - mount PCI conntectors...
- From: "Dr. Gerhart Hlawatsch" <ghl@scitel.de>
- To the folks looking for stradle - mount PCI conntectors...
- From: Lame Brooks-G14738 <Brooks_Lame-G14738@email.mot.com>
- RE: JTAG pins
- From: Ted Firlit <firlit@utmc.aeroflex.com>
- Intel 850 Chipset
- From: "Marco Serafini - QR s.r.l" <r&d@qrverona.it>
- Sequence ID
- From: "Kashif Ghafoor" <kasheeg@hotmail.com>
- From ASIS - : slot keying for 66MHz slots on CUR-DLS is wrong.
- From: "Austin Franklin" <darkroom@ix.netcom.com>
- PCI-SIG and "3GIO"
- From: "Tipley, Roger" <Roger.Tipley@compaq.com> (by way of Daniel Weaver <dan.weaver@znyx.com>)
- Multiple processors and pci-transparancy
- From: "Martijn Emons - Arcobel ASIC Design Centre B.V." <martijn.emons@arcobel.nl>
- Re: PCI enumeration and multiple processors
- From: "Martijn Emons - Arcobel ASIC Design Centre B.V." <martijn.emons@arcobel.nl>
- PCI enumeration and multiple processors
- From: fmnemeth@rockwellcollins.com
- RE: ASUS CUR-DLS 66MHz slot keying....did they screw it up?
- From: "Ingraham, Andrew" <Andrew.Ingraham@compaq.com>
- PCI undershoot/overshoot.
- From: Ramesh.Reddy@smartm.com
- RE: ASUS CUR-DLS 66MHz slot keying....did they screw it up?
- From: "mehrdad moradkhani" <mehrdad_am@hotmail.com>
- Re: ASUS CUR-DLS 66MHz slot keying....did they screw it up?
- From: "mehrdad moradkhani" <mehrdad_am@hotmail.com>
- Re: ASUS CUR-DLS 66MHz slot keying....did they screw it up?
- From: "mehrdad moradkhani" <mehrdad_am@hotmail.com>
- RE: ASUS CUR-DLS 66MHz slot keying....did they screw it up?
- From: "Austin Franklin" <austin@darkroom.com>
- RE: ASUS CUR-DLS 66MHz slot keying....did they screw it up?
- From: "Austin Franklin" <austin@darkroom.com>
- RE: ASUS CUR-DLS 66MHz slot keying....did they screw it up?
- From: "SHEU,PHILIP (HP-Cupertino,ex3)" <psheu@hp.com>
- ASUS CUR-DLS 66MHz slot keying....did they screw it up?
- From: "Austin Franklin" <darkroom@ix.netcom.com>
- Some question about Delayed transaction
- From: Yanzhe Liu <liu@gdatech.com>
- 3GIO Interest
- From: Alan.Deikman@znyx.com
- Re: Split Completions
- From: Amit Shah <ashah10@agere.com>
- Split Completions
- From: "Srividya Viswanathan" <srividya.viswanathan@idt.com>
- Transactions Rules
- From: "Kashif Ghafoor" <kasheeg@hotmail.com>
- Multiple delayed transactions
- From: "Kashif Ghafoor" <kasheeg@hotmail.com>
- Re: C/C++ to VHDL-Compiler
- From: wamnet <wamnet@gte.net>
- Re: Burst Read in slave mode
- From: "Randy.Dunlap" <rddunlap@osdlab.org>
- RE: Burst Read in slave mode
- From: "Fockler, Joe" <jfockler@chipdata.com>
- request for info on products that comply with low profile PCI card ECN (MD1 or MD2)
- From: "SHEU,PHILIP (HP-Cupertino,ex3)" <psheu@hp.com>
- RE: Burst Read in slave mode
- From: Lame Brooks-G14738 <Brooks_Lame-G14738@email.mot.com>
- C/C++ to VHDL-Compiler
- Transaction Ordering
- From: "Kashif Ghafoor" <kashif.ghafoor@and-or.com>
- Information Required
- From: "Kashif Ghafoor" <kashif.ghafoor@and-or.com>
- Question
- From: "Kashif Ghafoor" <kashif.ghafoor@and-or.com>
- RE: Burst Read in slave mode
- From: "Olaf Birkeland" <Olaf.Birkeland@fast.no>
- Burst Read in slave mode
- From: michael.pellegrino@modicon.com
- Question
- From: "Kashif Ghafoor" <kashif.ghafoor@and-or.com>
- Re: JTAG pins
- From: Ted Firlit <firlit@utmc.aeroflex.com>
- driver for 21554
- From: richard.snijders@philips.com
- Excess Retries to Bridge on Primary Side
- From: Pawitter Pal Singh <Pawitter.bhatia@dcmtech.co.in>
- RJ-45 jacks for PMC module ???
- From: Stuart Adams <sja@brightstareng.com>
- RE: JTAG pins
- From: Lame Brooks-G14738 <Brooks_Lame-G14738@email.mot.com>
- How ?
- From: "Ingemi, John" <John.Ingemi@compuware.com>
- remove
- From: "Janusz Kopczyk" <dsplab@wr.onet.pl>
- RE: JTAG pins
- From: "Olaf Birkeland" <Olaf.Birkeland@fast.no>
- Technology 3GIO Bus
- From: OSWALDO HIDALGO <OHIDALGO@unicon.com.pe>
- Re: pci retry
- From: Sanjay Cartic <scartic@ixiacom.com>
- RE: formula for adjusting pci clock?
- From: "Ingraham, Andrew" <Andrew.Ingraham@compaq.com>
- JTAG pins
- From: Ted Firlit <firlit@utmc.aeroflex.com>
- formula for adjusting pci clock?
- From: "Tom Curran" <tom_curran@memecdesign.com>
- RE: memory prefetchable
- From: "Naert, Hans" <hans.naert@barco.com>
- Re: memory prefetchable
- From: Carter Buck <CBuck@PLXTech.com>
- Fwd: Need device to assert latencies on bus
- From: Mike Dini <mdini@dinigroup.com>
- memory prefetchable
- From: "Marco Serafini - QR s.r.l" <r&d@qrverona.it>
- Need device to assert latencies on bus
- From: allan.boerner@conexant.com
- irdy on read
- From: Kevin Normoyle <Kevin.Normoyle@Sun.COM>
- Arbitration/Ordering of Intel Chipset
- From: "Hyun-Wook Jin" <hwjin@os.korea.ac.kr>
- RE: pci interrupt acknowledge cycle
- From: "Austin Franklin" <darkroom@ix.netcom.com>
- pci interrupt acknowledge cycle
- From: "BANESHWAR M SHANBHAG" <baneshwar.s@lycos.com>
- SSRAM question (off topic)
- From: "John W. Perry" <jperry@dinigroup.com>
- RE: PCI Signal clamping
- From: "Bernhard Andretzky" <andretzky@quicklogic.com>
- Re: PCI Signal clamping
- From: Neal Palmer <neal@dinigroup.com>
- Re: FW: Maximum Outstanding Split Transactions in PCI-X Configuration Control and Status Registers
- From: Amit Shah <ashah10@agere.com>
- Re: Maximum Outstanding Split Transactions in PCI-X Configuration Controland Status Registers
- From: "Richard Iachetta" <iachetta@us.ibm.com>
- FW: Maximum Outstanding Split Transactions in PCI-X Configuration Control and Status Registers
- From: "Srividya Viswanathan" <srividya.viswanathan@idt.com>
- Maximum Outstanding Split Transactions in PCI-X Configuration Control and Status Registers
- From: "Srividya Viswanathan" <srividya.viswanathan@idt.com>
- Diodes to Vi/o? RE: PCI Signal clamping
- From: Lame Brooks-G14738 <Brooks_Lame-G14738@email.mot.com>
- Re: PCI Signal clamping
- PCI Signal clamping
- From: Mark van Nobelen <Mark.van.Nobelen@chess.nl>
- Low Profile PCI
- From: "Taylor, Mike" <mike@exchange.SCOTLAND.NCR.com>
- Re: INT Lines vs IRQs
- From: Drew Eckhardt <drew@PoohSticks.ORG>
- INT Lines vs IRQs
- From: Chandrasekar Srinivasan <chandrasekar.s@dcmtech.co.in>
- Test Mail
- From: Chandrasekar Srinivasan <chandrasekar.s@dcmtech.co.in>
- RE: Device Select Timing
- From: "Taylor, Mike" <mike@exchange.SCOTLAND.NCR.com>
- RE: Device Select Timing
- From: "Fockler, Joe" <jfockler@chipdata.com>
- RE: Device Select Timing
- From: André David <Andre.David@cern.ch>
- Device Select Timing
- From: Siegfried Zeh <sizeit00@fht-esslingen.de>
- PCI Compliance Certificate by PCISIG?
- From: "Reichenbaecher, Olaf" <olaf.reichenbaecher@sci-worx.com>
- PMC clearances RE: Unidentified subject!
- From: Lame Brooks-G14738 <Brooks_Lame-G14738@email.mot.com>
- Unidentified subject!
- From: GAYATHRI PRABHU <gayathri@crlbel.ernet.in>
- Re: PCI Retry
- From: Amit Shah <ashah10@agere.com>
- PCI Retry
- From: r55017@email.sps.mot.com (Ryan Mcdaniel)
- IRQ and 21554.
- From: Christophe.LINDHEIMER@fr.thalesgroup.com
- Re: 21154
- From: Neal Palmer <neal@dinigroup.com>
- Re: Question about special cycle parity error
- From: "Weng Tianxiang" <WTX@umem.com>
- 21154
- From: "21cn" <ydtcn@21cn.com>
- Question about special cycle parity error
- From: Yanzhe Liu <liu@gdatech.com>
- RE: MASTER GNT# not being issued in response to REQ#
- From: "Hofmans, Kim" <kim.hofmans@barco.com>
- MASTER GNT# not being issued in response to REQ#
- From: "Daniel DeConinck" <daniel.deconinck@sympatico.ca>
- Master REQ# not receiving GNT#
- From: "Daniel DeConinck" <daniel.deconinck@sympatico.ca>
- RE: burst length
- From: "Hofmans, Kim" <kim.hofmans@barco.com>
- Archive
- From: wahab@karlnet.com (Mamdouh Wahab)
- burst length
- From: "Marco Serafini - QR s.r.l" <r&d@qrverona.it>
- July 27th PCI SIG membership meeting?
- From: "Snyder, Cary D. (Cahners)" <cds@mdr.cahners.com>
- looking for pci computers in VITA-32 PMC format
- From: Angel Guirao Elias <angel.guirao.elias@cern.ch>
- PCI bus monitor/cycle generator
- From: James Murray <jmurray@triscend.com>
- remove
- From: Fabrice Gens <gens@med.univ-tours.fr>
- PCI-Local-Bus-Switch Chip Manufacturer
- Re: How do I read the IRQ Routing Table with Assembler?
- From: Bob Smith <bsmith@sudleyplace.com>
- How do I read the IRQ Routing Table with Assembler?
- From: Siegfried Zeh <sizeit00@fht-esslingen.de>
- remove
- remove
- From: Hung Hingtung <tunghung@citicpacific.com>
- remove
- From: Shizuka Oda <shizuka@xilinx.com>
- remove
- From: Manish Gilani <manish.gilani@dcmtech.co.in>
- RE: remove
- From: Dustin_Brimberry@Dell.com
- Remove
- From: "Shruthi S" <shruthi.raghavan@wipro.com>
- remove
- From: Fabrice Gens <gens@med.univ-tours.fr>
- remove
- From: m.lagier@saunierduval.fr
- what is master retry timer?
- From: Sanjay Cartic <scartic@ixiacom.com>
- Re: How to access the pci configuration space?
- From: André David <Andre.David@cern.ch>
- Fwd: How to access the pci configuration space?
- From: Sagit Kaniel <sagit@jungo.com>
- Re: PCI to PCI bridges
- From: "Scott C. Karlin" <scott@CS.Princeton.EDU>
- PCI to PCI bridges
- From: "Andrew Krenz" <a.krenz@aristoslogic.com>
- Command Register IO and Mem Enable Bit
- From: Bert Marston <bert@quadic.com>
- RE: pci clock frequency
- From: "Ingraham, Andrew" <Andrew.Ingraham@compaq.com>
- How to access the pci configuration space?
- From: =?gb2312?B?zfXo6w==?= <wanghua@omc.pim.tsinghua.edu.cn>
- pci clock frequency
- From: "Yao Zehui" <ydtcn@21cn.com>
- RE: IO space devices
- From: Dave Chalfant <Dave_Chalfant@phoenix.com>
- RE: IO space devices
- From: "Austin Franklin" <darkroom@ix.netcom.com>
- Re: IO space devices
- From: "Kevin Sharpe" <kevin.sharpe@btinternet.com>
- Re: IO space devices
- From: "Marco Serafini - QR s.r.l" <r&d@qrverona.it>
- Re: IO space devices
- From: Dimiter Popoff <tgi_earth@yahoo.com>
- IO space devices
- From: r55017@email.sps.mot.com (Ryan Mcdaniel)
- Re: AD_OE timing
- From: Manfred Kuhland <man@atlantek.com.au>
- Re: AD_OE timing
- From: "Khan Kibria" <kkibria@iss-us.com>
- RE: AD_OE timing
- From: Daniel Weaver <dan.weaver@znyx.com>
- Re: AD_OE timing
- From: James Murray <jmurray@triscend.com>
- AD_OE timing
- From: "Weng Tianxiang" <WTX@umem.com>
- State of Arbiter GNT during PCI Reset
- From: James Murray <jmurray@triscend.com>
- Arbitration Code example
- From: James Murray <jmurray@triscend.com>
- RE: FIFO in PCI memory space
- From: Richard Walter <rwalter@brocade.com>
- RE: FIFO in PCI memory space
- From: Sanjay Cartic <scartic@ixiacom.com>
- FIFO in PCI memory space
- Re: Using Multiple BAR's
- From: Ivor Bowden <ivor@peritek.com>
- RE: Using Multiple BAR's
- From: "Austin Franklin" <darkroom@ix.netcom.com>
- RE: RE: Using Multiple BAR's
- From: Lame Brooks-G14738 <Brooks_Lame-G14738@email.mot.com>
- Re: Using Multiple BAR's
- From: Drew Eckhardt <drew@PoohSticks.ORG>
- Re: Using Multiple BAR's
- From: fmnemeth@rockwellcollins.com
- Re: Using Multiple BAR's
- From: "Weng Tianxiang" <WTX@umem.com>
- RE: Using Multiple BAR's
- From: "Bill Peet" <peet@rtviz.com>
- Using Multiple BAR's
- From: "Bearzi, Anthony" <abearzi@harris.com>
- IDE bridge chips, address decoding and byte enables
- From: r55017@email.sps.mot.com (Ryan Mcdaniel)
- Re: access PCI memory from DOS, or linux?
- From: André David <Andre.David@cern.ch>
- RE: access PCI memory from DOS, or linux?
- From: Gord Wait <Gord_Wait@spectrumsignal.com>
- Re: access PCI memory from DOS
- From: lecos@samsung.co.kr
- Re: access PCI memory from DOS
- From: Ivor Bowden <ivor@peritek.com>
- access PCI memory from DOS
- From: JohanHZ@Sycron-IT.com
- Re: PCI2.2 Master Transaction Claiming
- From: "Schneider, Dave" <Dave.Schneider@emulex.com>
- RE: PCI2.2 Master Transaction Claiming
- From: Barry Davis <BDavis@nvidia.com>
- Re: PCI2.2 Master Transaction Claiming
- From: "Richard Iachetta" <iachetta@us.ibm.com>
- PCI2.2 Master Transaction Claiming
- From: Bert Marston <bert@quadic.com>
- RE: PCI2.2 Master Transaction Claiming
- From: Richard Walter <rwalter@brocade.com>
- unsuscribe
- From: "Graziella COMISSO" <gcomisso@midisystem.fr>
- Re: VHDL Model For PLX ?
- From: Carter Buck <CBuck@PLXTech.com>
- VHDL Model For PLX ?
- From: "Thomas Ebert" <te@wiese.de>
- pci master retry timeout value
- From: Sanjay Cartic <scartic@ixiacom.com>
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