[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: what in case of address parity error? (fwd)

> > In case of a data parity error, PERR# must be asserted.
> Parity checking is not must, only generation is must. PERR# may be
asserted only if
> Parity Error Response bit (#6) is set. 
Yes, I know. I did set the PERR bit in the command register. So I have to
assert PERR# when a data parity error has occured.
> > In case of an address parity error, SERR# must be asserted.
> Again it is not must. It may be asserted only if Parity Error Response
and SERR# enable
> bits are set.
> Please also note that SERR# is only one way of communicating a system
level error.
> See and (PCI 2.1)

I didn't set the SERR bit becuz I don't want to use SERR#.
But when a address parity error has occured, the only way to tell the
initiator is to assert SERR#.

Please note I don't have actually the SIG PCI specs 2.1.
I'm using the book PCI system architecture(covers the 2.1 specs), it says:

"If however, it results in a miscompare by any of the targets, the address
and/or command were corrupted in flight. This is considered to be a
destabilizing event in the PCI environment. The initiator is reaching out
and touching someone it never meant to touch or is touching them in a way
it never meant to. SERR# is the reporting mechanism"

So my questions are :
how do I tell the initiator an address parity error occured without using  

Can I use a target abort after detecting a address parity error ?

PCI system architecture : 

"One of the ways a target can respond to a
parity error detected at the completion of the address phase is to issue a
target abort in addition to its assertion of SERR#"

But I don't have to assert SERR# for a target abort, so I assume that I
can use a target abort without SERR#. 
So this would solve my problem with the address phase error, am I right ?

Thanks in advance,