PCI Bus Master memory read commands

["Phil Hallmark" <phil.hallmark@analog.com>]

Hello PCI designers,

I am implementing a PCI bus master device and would appreciate
some input on the memory read commands. If I want to burst-read
main memory residing on the host bus, I am under the assumption
that the host/pci bridge will translate my normal memory read
commands into "Memory Read Line" or "Memory Read Multiple"
("MRL" or "MRM") commands on the host side (unless the host/pci
bridge does not support MRL/MRM commands). For the sake of this
discussion, I am assuming that my device is on PCI bus 0 (one 
bridge removed from the host bus), and main memory is marked 
prefetchable. Note that I am not interested in cache coherency
issues, I just want to get contents of main memory into my on-chip
fifo as quickly as possible.

I have 2 questions on this topic:

1) Will the host/pci bridge take care of the translation of my
   normal "memory read" commands to MRL/MRM commands on the host
   side, or do I need to specifically issue the MRL/MRM commands?

2) In general, what are good practices to follow to ensure good,
   sustained burst rates for memory reads? I know that writes are
   better than reads due to write-posting, but I am constrained to
   be a master and do burst reads in this case.

Thanks,
Phil Hallmark

__________________________________________________________________
Phil Hallmark					 ph:  512-418-0003
Analog Devices					 fax: 512-418-0006
6805 N. Capital of Tx Highway	          phil.hallmark@analog.com
Suite 250
Austin, Tx. 78731


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