Re: PCI Bus Master memory read commands

["Monish Shah" <monish@mcsy2.fc.hp.com>]

On Jul 25,  2:34pm, Phil Hallmark wrote:
> I have 2 questions on this topic:
>
> 1) Will the host/pci bridge take care of the translation of my
>    normal "memory read" commands to MRL/MRM commands on the host
>    side, or do I need to specifically issue the MRL/MRM commands?

You *have* to issue MRL/MRM as appropriate.  If you issue an MR, how is the
bridge supposed to know that you intend to do a long burst?  It can't.
That's why MRL and MRM exist in the first place.

> 2) In general, what are good practices to follow to ensure good,
>    sustained burst rates for memory reads?

Design your device so you're capable of doing long bursts.  This requires
storage in you chip, so you have to make a careful trade-off.  If you have
too little storage, the bursts will not be long enough and performance will
suffer.  If you have too much storage, you've got unnecessary cost.  Here's
how I'd size that storage:

# of bytes of storage = (required bandwidth) * (max. BG to BG latency)

Max.  BG to BG latency refers to the maximum amount of time you expect to
see between successive bus grants to your device, assuming you request is
asserted pretty much all the time.  While there is no spec for this, if you
design for 40 microseconds, you're pretty safe.  (40 us is my rough guess.
You're welcome to use a different number if you have a better guess.)  The
required bandwidth is a function of your application, of course.

All this assumes that you want to achieve your performance goal in a system
while there is other bus activity going on.  If you only need to achieve
this when there is nothing else going on, you'd get away with less
storage.

> Thanks,
> Phil Hallmark

Monish Shah
Hewlett Packard


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