Re: PCI Bus Master memory read commands

["Frank Hady" <Frank_Hady@ccm.jf.intel.com>]

Text item: 

     As a PCI bus master you should issue MR, MRL and MRM commands to give
     the bridge chip a clue of the size burst you intend to complete.  You 
     don't have to use anything but MR for memory reads, but if you don't 
     your performance may suffer greatly.  See the spec and 
     www-cs.intel.com/oem_developer/chipsets/pci/general/pci001.htm for an
     explanation on why/how to use these commands.
     
     Frank Hady
     Intel Corporation


______________________________ Reply Separator
_________________________________
Subject: PCI Bus Master memory read commands
Author:  pci-sig-request@znyx.com at SMTPGATE
Date:    7/25/96 2:34 PM


Hello PCI designers,

I am implementing a PCI bus master device and would appreciate
some input on the memory read commands. If I want to burst-read
main memory residing on the host bus, I am under the assumption
that the host/pci bridge will translate my normal memory read
commands into "Memory Read Line" or "Memory Read Multiple"
("MRL" or "MRM") commands on the host side (unless the host/pci
bridge does not support MRL/MRM commands). For the sake of this
discussion, I am assuming that my device is on PCI bus 0 (one
bridge removed from the host bus), and main memory is marked
prefetchable. Note that I am not interested in cache coherency
issues, I just want to get contents of main memory into my on-chip
fifo as quickly as possible.

I have 2 questions on this topic:

1) Will the host/pci bridge take care of the translation of my
   normal "memory read" commands to MRL/MRM commands on the host
   side, or do I need to specifically issue the MRL/MRM commands?

2) In general, what are good practices to follow to ensure good,
   sustained burst rates for memory reads? I know that writes are
   better than reads due to write-posting, but I am constrained to
   be a master and do burst reads in this case.

Thanks,
Phil Hallmark

__________________________________________________________________
Phil Hallmark                          ph:  512-418-0003
Analog Devices                          fax: 512-418-0006
6805 N. Capital of Tx Highway               phil.hallmark@analog.com
Suite 250
Austin, Tx. 78731

Text item: External Message Header

The following mail header is for administrative use
and may be ignored unless there are problems.

***IF THERE ARE PROBLEMS SAVE THESE HEADERS***.

To: Mailing List Recipients <pci-sig-request@znyx.com>
Resent-Sender: pci-sig-request@znyx.com
Precedence: list
X-Loop: pci-sig@znyx.com
X-Mailing-List: <pci-sig@znyx.com> archive/latest/3301
Resent-Message-Id: <"PqVoI.0.hN.3yyzn"@dart>
Cc: pci_sig@ccm.jf.intel.com, art.piejko@analog.com
Subject: PCI Bus Master memory read commands
Message-Id: <9607251934.AA20007@persephone.spd.analog.com>
From: phil.hallmark@analog.com (Phil Hallmark)
Date: Thu, 25 Jul 96 14:34:38 CDT
Resent-Date: Thu, 25 Jul 96 14:34:38 CDT
Received: by znyx.com (5.65/1.35)
     id AA01557; Thu, 25 Jul 96 12:48:56 -0700
Received: from znyx.com by netcomsv.netcom.com with SMTP (8.6.12/SMI-4.1)
     id MAA11768; Thu, 25 Jul 1996 12:49:26 -0700
Received: from netcomsv.netcom.com (uumail1.netcom.com [163.179.3.50]) by
mailba
g.jf.intel.com (8.7.4/8.7.3) with SMTP id NAA17618; Thu, 25 Jul 1996
13:00:37 -0
700 (PDT)
Resent-From: pci-sig-request@znyx.com
Received: from mailbag.jf.intel.com (root@mailbag.jf.intel.com
[134.134.248.4])
by relay.jf.intel.com (8.7.4/8.7.3) with ESMTP id NAA01585; Thu, 25 Jul
1996 13:
01:37 -0700 (PDT)
Return-Path: pci-sig-request@znyx.com


���