re: PCI Bus Master memory read commands

["Alex Predtechenski" <Alexei.Predtechenski@amd.com>]

>I was under the impression that bridges incorporate prefetch buffers
>that do in fact prefetch more data than the master asks for. Then if
>the master doesn't use the data it is discarded by the bridge. This
>assuming that main memory on the host side is prefetchable.
>
>1) Is a typical host/PCI bridge limited to only access the exact 
>   amount of main memory data that a PCI-side master asks for 
>   during an MR command?
>
>2) If a PCI master uses Memory Read Line (MRL) or Memory Read 
>   Multiple (MRM) commands to access main memory, can it attempt to
>   continue a single burst indefinitely (assuming it observes the 
>   4k page boundary rules), or is the burst length limited by a 
>   preset "cache line" length? If limited, where does the line 
>   length information reside and how does the PCI master access it?
>

"Typical" Triton bridges (FX,VX,HX) are capable to prefetch data. At least,
the AMCC master (it has only MR command implemented) can read from the host
memory in bursts -1-1-1-1-1- (no wait states between data phases) almost
indefinitely. The same is true when using HP 2910 PCI Bus Exerciser.
UMC888x
chipset will do burst reads, but the data pattern will look like
-5-2-2-2-5-2-2-2-. These 5 states per data phase, as I guess, are related
to
the cache line size.

Sincerely,
 
- Alex
_________________________              _______
Alex Predtechenski                     \____  | Advanced  
Systems Engineering                    /|   | |    Micro  
Multimedia Products/IND               | |___| |  Devices              
(512)602-3567                         |____/ \|  
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