decreasing bus clok speed

["Rafiki Kim Hofmans" <tw38966@is1.bfu.vub.ac.be>]

Hi,

sorry if this question has already beenasked before,

but is there a way to decrease the bus clock frequency ?

The reason for this is that I will use a 2 layer PCB for testing my
fpga-pci interface.
I've already looked in the bios setup, but I haven't noticed a clock
divider so far (like CLKI/4 in the older motherboards)

Thanks in advance

Kim


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