re: PCI Bus Master memory read commands

["Tom Keaveny" <tak@core.rose.hp.com>]

> 1) Is a typical host/PCI bridge limited to only access the exact 
>    amount of main memory data that a PCI-side master asks for 
>    during an MR command?
> 
according to section 3.1.1, PCI v2.1 (page 22)

	"The Memory Read command ... The target is free to do an anticipatory
	read for this command only if it can guarantee that such a read will
	have no side effects."

the section also describes coherency requirements for
pre-fetched/anticipatory
buffers.  Note that MRM and MRL are semantically equivalent to MR in these
respects, according to the spec.

> 2) If a PCI master uses Memory Read Line (MRL) or Memory Read 
>    Multiple (MRM) commands to access main memory, can it attempt to
>    continue a single burst indefinitely (assuming it observes the 
>    4k page boundary rules), or is the burst length limited by a 
>    preset "cache line" length? If limited, where does the line 
>    length information reside and how does the PCI master access it?
> 

I don't see any explicit limitations in the spec.  As far as cache line
sizes are concerned, the CacheLine Size configuration register contains
this data.  Note, that loss of GNT# and expiration of the latency timer
is supposed to terminate a burst.  See section 3.5.3 for the ground rules.

Also, note that page boundaries aren't necessarily cast in concrete
or consistent across all PCI-based systems...

==
tom keaveny
hewlett packard co.	disclaimer:	"opinions are my own and not 
					necessarily that of Hewlett Packard"


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