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Re: decreasing bus clok speed

At 06:10 PM 7/29/96 +0200, you wrote:
>
>but is there a way to decrease the bus clock frequency ?
>
>The reason for this is that I will use a 2 layer PCB for testing my
>fpga-pci interface.
>I've already looked in the bios setup, but I haven't noticed a clock
>divider so far (like CLKI/4 in the older motherboards)

If you are not afraid of making some patches on your MB, it is easy.

First, the main MB PLL may have (usually undocumented) settings for CPU 
clock of 20 MHz, or even much lower. It depends on the PLL device used. 
On most PC-core chipsets this will give 
you the same PCI clock. There should be no problem with CPU since normally
they have a reasonable low limit on input frequency, down to 8 MHz (at
least
AMD486 and amd5x86).

If there is no jumpers to set the lower frequency, you may just cut off
this
CPUCLK
and pass it through a custom frequency divider. Effect will be the same -
low bus
speed. Of course, the CPU will run proportionally slow.

Hope this helps,


- Alex
_________________________              _______
Alex Predtechenski                     \____  | Advanced  
Systems Engineering                    /|   | |    Micro  
Multimedia Products/IND               | |___| |  Devices              
(512)602-3567                         |____/ \|  
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