re: PCI Bus Master memory read commands

["Jim Holeman" <holeman@lumeria.mpd.tandem.com>]

Tom Keaveny <tak@core.rose.hp.com> wrote  
> 
> I don't see any explicit limitations in the spec.  As far as cache line
> sizes are concerned, the CacheLine Size configuration register contains
> this data.  Note, that loss of GNT# and expiration of the latency timer
> is supposed to terminate a burst.  See section 3.5.3 for the ground
rules.
> 
> Also, note that page boundaries aren't necessarily cast in concrete
> or consistent across all PCI-based systems...
> 
 
Tom notes in his reply above that page boundaries are neither fixed, nor
consistent across PCI-based systems......
What about cacheline sizes?  Are they fixed in any way?  What is the norm?
What is the trend?


  holeman

 
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  Jim Holeman                                          Tandem Computers,
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