Re: PCI Bus Master memory read commands

["Monish Shah" <monish@mcsy2.fc.hp.com>]

On Jul 30, 10:30am, Jim Holeman wrote:
...

> Tom notes in his reply above that page boundaries are neither fixed, nor
> consistent across PCI-based systems......
> What about cacheline sizes?  Are they fixed in any way?

No.

> What is the norm?

32 bytes, as far as I know.

> What is the trend?

It is increasing.  Some high-end systems have 256 byte cachelines today.  I
expect 64 bytes to become the norm in a few years.

The lesson is: it would be a good idea to design your card to understand
larger than 32 byte cacheline sizes if you implement the cacheline size
register at all.

>  
____________________________________________________________________________

>
>   Jim Holeman                                          Tandem Computers,
Inc.
>   (512) 432-8755 (fax 8247)                            14231 Tandem
Boulevard
>   holeman@isd.tandem.com                               Austin, Tx
78728-6699
>
>   "A gentle answer turns away wrath"

Monish Shah
Hewlett Packard

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