re: PCI Bus Master memory read commands

["Tom Keaveny" <tak@core.rose.hp.com>]

> What about cacheline sizes?  Are they fixed in any way?  What is the
norm?
> What is the trend?
> 

Line size can vary with a given system, and tends to grow larger
with system evolution.   For PC's, 16 and 32 byte lines sizes are 
the norm, from what I understand.  For various RISC-based systems,
I believe the size is larger.

>From a PCI standpoint, I suspect that there may be some point where
a given add-on device might have to switch from cache-line (e.g.
MRL) to multi-word (MRM) if they do not have sufficient resources
to deal with the cache-line-size du jour (which can be as large
as 1Kbyte)

==
tom keaveny
hewlett packard	- DISCLAIMER	"comments are my own and not
				necessarily that of Hewlett Packard"


©˜†