Re: IRDY# in multiple data Special cycle Transaciton

["Shivakumar S. Chonnad" <shiv@Synopsys.COM>]

Hi,

Can anyone clarify regarding the following sentence in the PCI 2.1 spec
pp83
regarding the Multiple data phase Special cycle transaction:

"The target must latch data on the first clock IRDY# is asserted for each
 piece of data transferred."

As the above mentions latching data on *first* clock of IRDY#, does the
above 
imply that the IRDY# *must* be deasserted for each additional piece of data

transferred ?

Any response will be appreciated.

Thanks in advance,
Shiv. 


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