Re: PCI pinout

["Andy Ingraham" <ingraham@wrksys.ENET.dec.com>]

> In Solari and Willse's PCI book, there is a picture with the "suggested"
> PCI pinout (page 423).

I don't have that book here, but am looking at the suggested pinout in
Figure 4-10 in the PCI spec.

>   I noticed that the upper and lower bytes of the
> AD bus are kept together left and right edge of the chip.  Is there
> a reason for that?

The intent is to show a suggested _ordering_ of pins.  The fact that the
package corner falls between IDSEL and AD[23] in the illustration is
inconsequential.

> I am working on a PCI pinout for a smallish package and I will need
> to move some of the AD pins from the bottom edge to the left and right.
> Any comments would be appreciated.  In general, any feedback on
> pinout and the impact on the board design would be useful to me.  Thanks.

There's no reason to follow their pinout suggestion, other than the fact
that it tends to minimize trace lengths and make routing easier between
the IC package and the PCI connector.  Get someone to run a trial board
route while you choose the pinning.

Trace lengths on the lower 32-bit signals and most control signals must
be less than 1.5" long.  If you have 64-bit PCI, the upper bits must be
less than 2" long, so they are further away on the recommended pinout. 
The clock must be 2.5" +/- 0.1".  JTAG, INTn#, and RST# don't have
controlled lengths so they can be further away.

You may also need to consider what goes on inside your IC when choosing
the pinout.

Regards,
Andy Ingraham


¬\J