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Re: IRDY# in multiple data Special cycle Transaciton

Shiv wrote:
> Can anyone clarify regarding the following sentence in the PCI 2.1 spec
> regarding the Multiple data phase Special cycle transaction:
> "The target must latch data on the first clock IRDY# is asserted for each
>  piece of data transferred."
> As the above mentions latching data on *first* clock of IRDY#, does the
> imply that the IRDY# *must* be deasserted for each additional piece of
> transferred ?
I would venture that the intention is to allow the initiator to continue
to assert IRDY# for a multiple-data-phase transaction, or not, depending
on whether it needs to insert "wait states".  If the initiator needs one
or two (or few) cycles to get the next piece of data ready, then IRDY#
will cycle on and off.  If the initiator is prepared to feed the data onto
the PCI bus as fast as the PCI bus cycles, then IRDY# would stay asserted.

The deal is that the targets are sampling IRDY# on each clock, and should
latch data if it is asserted, or wait if it is not.  They really don't
have the choice, for instance, of inserting target waits because Special
Cycle transactions are a kind of poor man's broadcast protocol.  To make
this work, all the targets that would care about this kind of cycle must
deal with it as fast as the fastest possible target on the system, i.e.,
with zero target wait states.

Perhaps this is a vast oversimplification of what goes on, but hopefully
this describes the basic idea.


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