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Re: JTAG/Boundary Scan

To: "Mailing List Recipients" <pci-sig-request@znyx.com>
Subject: Re: JTAG/Boundary Scan
From: "Devendra K Tripathi" <tripathi@Synopsys.COM>
Date: Sat, 3 Aug 1996 04:56:18 -0700
Cc: <pci-sig@znyx.com>

The two suggestions apply to two different situations. In case you are
implementing a
board, you need to tie input to output so that chain can be maintained. If
it is a 
planner implementation (may be motherboard), it means the system itself is
not 
implemeting JTAG. In this case you need to follow next suggestion (so that
other 
boards which might be implementing it get proper signal levels).

Thanks,
Tripathi.


Ô¬›

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