[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: PCI 2.0 (33MHz) support for maximum burst data transfer
- To: Mailing List Recipients <pci-sig-request@znyx.com>
- Subject: Re: PCI 2.0 (33MHz) support for maximum burst data transfer
- From: Bruce Young <Bruce_Young@ccm.jf.intel.com>
- Date: Mon, 05 Aug 96 18:25:00 PDT
- Resent-Date: Mon, 05 Aug 96 18:25:00 PDT
- Resent-From: pci-sig-request@znyx.com
- Resent-Message-Id: <"tq0A92.0.Q-3.H3g1o"@dart>
- Resent-Sender: pci-sig-request@znyx.com
---------------------------- Forwarded with Changes ---------------------------
From: pci-sig-request@znyx.com at SMTPGATE
Date: 8/5/96 4:51PM
*To: pci-sig-request@znyx.com at SMTPGATE
Subject: PCI 2.0 (33MHz) support for maximum burst data transfer from
-------------------------------------------------------------------------------
This is relatively easy to calculate but is system dependent.
Assuming that the system allows long bursts with no wait states (as Intel's
430FX,HX,VX and 440FX PCISets do) the calculation is shown below.
Max BW = (Burst)/((Initial Latency + Burst/4 + 1) * 30 ns)
Burst is burst length in bytes and the "1" is for bus turn-around
With Intel chipsets that have approx 3 clock initial latency for writes and 10
clocks for reads (This is approx and depends on the chipset and cache condition
- Your mileage may vary ;-) this gives a maximum bandwidth of
40 bytes 60 bytes 128 bytes
Disk Reads (PCI Writes) 95 MB/s 105 MB/s 118 MB/s
Disk Writes (PCI Reads) 58 MB/s 71 MB/s 95 MB/s
As you can see, the burst length required for efficient use of the PCI bus is
directly dependent on the initial latency. Since read latency is nearly always
higher than write latency, long bursts are especially important. This is yet
another reason to use Memory Read Line and Memory Read Multiple when
appropriate.
Of course this is a maximum BW calculation and how close to this you could get
will depend on how much other activity is going on both on the PCI bus and in
the CPU.
-Bruce Young
Intel Corporation
On the net I speak for myself, not Intel.
Hello,
Has anyone done some analysis on what the maximum burst data transfer
rate from disk drive the PCI memory writes/reads can support? What i
know is that PCI 2.0 (33MHz) can support a burst transfer of up to
132MB/sec, and realistically can sustain 70 to 80MB/sec.
Suppose you have a Ultra-SCSI drive that can burst transfer to the
host PCI SCSI HAC (Host Adapter Card) at 40 to 80MB/sec but only at
a size of 40 to 60 bytes. Would PCI 2.0 (33MHz) have any PCI memory
writes/reads bottle necking problem with this type of short (very
short) burst data transfer?
Thank you very much,
-gshin
å t c