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Cache Line Size register
- To: Mailing List Recipients <pci-sig-request@znyx.com>
- Subject: Cache Line Size register
- From: Ali Najafi <alinajafi@aztech.com.sg>
- Date: Tue, 6 Aug 1996 17:39:34 +0800
- Resent-Date: Tue, 6 Aug 1996 17:39:34 +0800
- Resent-From: pci-sig-request@znyx.com
- Resent-Message-Id: <"RDDiA.0.f95.DNn1o"@dart>
- Resent-Sender: pci-sig-request@znyx.com
Hi all,
Cache Line Size register should contain the system's cache line size. Who
writes that information into it?
Any information appreciated.
Thanks,
Ali Najafi
ë @ /