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RE: Cache Line Size register
- To: Mailing List Recipients <pci-sig-request@znyx.com>
- Subject: RE: Cache Line Size register
- From: ingvar_berg@x400.icl.co.uk
- Date: Tue, 6 Aug 1996 12:20:49 +0100
- Priority: NORMAL
- Reply-To: ingvar_berg@x400.icl.co.uk
- Resent-Date: Tue, 6 Aug 1996 12:20:49 +0100
- Resent-From: pci-sig-request@znyx.com
- Resent-Message-Id: <"bvscp.0._N5.Uno1o"@dart>
- Resent-Sender: pci-sig-request@znyx.com
Ali Najafi wrote:
>Cache Line Size register should contain the system's cache line size. Who
>writes that information into it?
The system bios writes it during configuration (POST).
/Ingvar
ì À ®