[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: i960RP - host downloading code
Text item:
Please see comments below:
thx
byron gillespie
i960 RP Technical Marketing
intel
______________________________ Reply Separator _________________________________
Subject: i960RP - host downloading code
Author: pci-sig-request@znyx.com at SMTPGATE
Date: 8/6/96 8:26 AM
Hello everybody,
This mail is specificly regurding the i960RP PCI bridge. If anyone has
an answer, it is welcomed.
I am working on a PCI design based on the i960RP, and
I intend to control the device from a PCI host. The fact that the core
proccesor code can be downloaded from the host implies that it is
possible to access the local bus while keeping the core proccesor in
reset state. However, there are several difficulties and contradictions
in the user manual that are not clear to me:
1) PMCON is not accessible through ATU, (This I conclude from the fact
that it is not a PMMR - Peripheral Memory Mapped Register). Thus, it
cannot be controlled by a PCI host. If we add the fact that the PMCON
is configured to 8 bit width by power up defualt, it certainly looks like
a problem to me.
>>
>> The PMCON is not accessible via the ATU. It is a i960 JX Internal
>> MMR. However, it is not a problem. The PMCON does default to an
>> 8-bit region, however, the first thing the 960 does after reset is
>> de-asserted is read the initialization-boot-record (IBR). This record
>> contains a PMCON (accessible via a 32-bit bus or 8-bit bus) and is
>> used to configure the Jx Bus Controller for the remainder of the
>> accesses in the address region without any bus width problems. The
>> reason it does not matter the what the bus width is when accessing
>> the IBR is because of the addressing used. It always accesses the low
>> byte of a word. The data is present on the correct byte lanes
>> regardless of 8-bit or 32-bit memory.
>>
2) The ATU limit register and translate register are read only registers,
so I don't understand how do I control them.
>>
>> Yes they are read only ...VIA PCI Configuration Cyles. If
>> you do inbound address translation (ie. memory read or
>> memory write cycles based on the default translation mechanism
>> you will accesses the MMR's and have full READ/WRITE capabilities
>> as the JX core.
>>
3) The PMMR are mapped to low local memory addresses, while the physical
memory should be mapped to high local memory addresses. This means
that every time PCI host needs to access a PMMR (for example, the DMA
controller registers) and then the physical memory (in order to build
the DMA chain buffers), it must switch the ATU translate register.
If this is correct, it could be a serious problem in a multitasking
operating system.
>>
>> The DMA Control registers are intended to be controlled by the
>> JX core executing software. Not by a PCI master. That is why
>> it is difficult.
>>
4) Can I get a source code example of a host downloading code? Maybe
this would help me understand some of the problems, along with
specific answers to the above questions.
>>
>> I will check and see if we have something available.
>>
Thanks in advance,
=========================================================================
Noam Efrati | e-mail: noam@terra.co.il
Terra computers ltd. | phone : 972-7-467502
6 Ashuach st., Omer, | fax : 972-7-467475
84965 Israel |
=========================================================================
Text item: External Message Header
The following mail header is for administrative use
and may be ignored unless there are problems.
***IF THERE ARE PROBLEMS SAVE THESE HEADERS***.
To: Mailing List Recipients <pci-sig-request@znyx.com>
Resent-Sender: pci-sig-request@znyx.com
Precedence: list
X-Loop: pci-sig@znyx.com
X-Mailing-List: <pci-sig@znyx.com> archive/latest/3389
Resent-Message-Id: <"z-wBu.0.bP4.TVj1o"@dart>
Content-Type: TEXT/PLAIN; charset=US-ASCII
Mime-Version: 1.0
Message-Id: <Pine.SGI.3.91.960806082422.6098A-100000@genie.terra.co.il>
Subject: i960RP - host downloading code
X-Sender: noam@genie.terra.co.il
From: Noam Efrati <noam@genie.terra.co.il>
Date: Tue, 6 Aug 1996 08:26:05 +0300 (IDT)
Resent-Date: Tue, 6 Aug 1996 08:26:05 +0300 (IDT)
Received: by znyx.com (5.65/1.35)
id AA18107; Mon, 5 Aug 96 22:30:46 -0700
Received: from znyx.com by netcomsv.netcom.com with SMTP (8.6.12/SMI-4.1)
id WAA10774; Mon, 5 Aug 1996 22:32:18 -0700
Received: from netcomsv.netcom.com (uumail1.netcom.com [163.179.3.50]) by mailba
g.jf.intel.com (8.7.4/8.7.3) with SMTP id WAA02030; Mon, 5 Aug 1996 22:39:15 -07
00 (PDT)
Resent-From: pci-sig-request@znyx.com
Received: from mailbag.jf.intel.com (root@mailbag.jf.intel.com [134.134.248.4])
by relay.jf.intel.com (8.7.4/8.7.3) with ESMTP id WAA12368; Mon, 5 Aug 1996 22:4
0:10 -0700 (PDT)
Return-Path: pci-sig-request@znyx.com
ñ ¼ ©