Re: i960RP - host downloading code

[Noam Efrati <noam@genie.terra.co.il>]

=========================================================================
Noam Efrati                    | e-mail: noam@terra.co.il  
Terra computers ltd.	       | phone : 972-7-467502		 
6 Ashuach st., Omer,           | fax   : 972-7-467475
84965 Israel                   |
=========================================================================


> 
> Text item: 
> 
>      Still I am confused - 
>        
>      
>      see details below...  
>      
>      noam.
> 
> 
> ______________________________ Reply Separator _________________________________
> Subject: i960RP - host downloading code
> Author:  pci-sig-request@znyx.com at SMTPGATE
> Date:    8/6/96 8:26 AM
> 
> 
> Hello everybody,
>      
> This mail is specificly regurding the i960RP PCI bridge. If anyone has 
> an answer, it is welcomed.
>      
> I am working on a PCI design based on the i960RP, and
> I intend to control the device from a PCI host. The fact that the core 
> proccesor code can be downloaded from the host implies that it is 
> possible to access the local bus while keeping the core proccesor in 
> reset state. However, there are several difficulties and contradictions 
> in the user manual that are not clear to me:
>      
> 1) PMCON is not accessible through ATU, (This I conclude from the fact 
> that it is not a PMMR - Peripheral Memory Mapped Register). Thus, it 
> cannot be controlled by a PCI host. If we add the fact that the PMCON
> is configured to 8 bit width by power up defualt, it certainly looks like 
> a problem to me.
> 
> >>
> >> The PMCON is not accessible via the ATU.  It is a i960 JX Internal
> >> MMR.  However, it is not a problem.  The PMCON does default to an
> >> 8-bit region, however, the first thing the 960 does after reset is
> >> de-asserted is read the initialization-boot-record (IBR).  This record
> >> contains a PMCON (accessible via a 32-bit bus or 8-bit bus) and is
> >> used to configure the Jx Bus Controller for the remainder of the 
> >> accesses in the address region without any bus width problems.  The
> >> reason it does not matter the what the bus width is when accessing
> >> the IBR is because of the addressing used.  It always accesses the low
> >> byte of a word.  The data is present on the correct byte lanes 
> >> regardless of 8-bit or 32-bit memory.
> >>
> 
> >> >> If the IBR is read after reset is de-asserted, then how 
> >> >> does the host perfome code loading to 32 bit ram prior to
> >> >> de-asserted reset? This is not possible if the memory 
> >> >> controller is accesing an 8 bit area (as the PMCON 
> >> >> default)...
>
>      
> 2) The ATU limit register and translate register are read only registers, 
> so I don't understand how do I control them.
> 
> >>
> >> Yes they are read only ...VIA PCI Configuration Cyles.  If
> >> you do inbound address translation (ie. memory read or
> >> memory write cycles based on the default translation mechanism
> >> you will accesses the MMR's and have full READ/WRITE capabilities
> >> as the JX core.
> >>
>
> >> >> a) Still It is a problem: if the limit register defualt is set
> >> >>    to 4k , then the BIOS power-up routines will initiate the 
> >> >>    BAR of the varios devices accordingly. If the driver needs 
> >> >>    more then 4k, it must change the limit register, but this
> >> >>    can be done after the BIOS power-up sequnce, so there is not
> >> >>    much that can be done, unless I am not missing something...
> >> >>
> >> >> b) In page 16-5 in the user manual, it is said that the first 4k
> >> >>    of the translation window is directed to the messaging unit.
> >> >>    If this is so, and if the limit register default is set to 4k,
> >> >>    how can the MMR's be accessed, based on the default translation
> >> >>    mechanism ?
> >> >> 

      
> 3) The PMMR are mapped to low local memory addresses, while the physical 
> memory should be mapped to high local memory addresses. This means
> that every time PCI host needs to access a PMMR (for example, the DMA 
> controller registers) and then the physical memory (in order to build 
> the DMA chain buffers), it must switch the ATU translate register.
> If this is correct, it could be a serious problem in a multitasking 
> operating system.
> 
> >>
> >> The DMA Control registers are intended to be controlled by the 
> >> JX core executing software.  Not by a PCI master.  That is why
> >> it is difficult.
> >>
> 
>      
>      
> 4) Can I get a source code example of a host downloading code? Maybe 
> this would help me understand some of the problems, along with 
> specific answers to the above questions.
> 
> >> 
> >> I will check and see if we have something available.
> >>
>      
> 
> Thanks in advance,
>      
> ========================================================================= 
> Noam Efrati                    | e-mail: noam@terra.co.il
> Terra computers ltd.           | phone : 972-7-467502 
> 6 Ashuach st., Omer,           | fax   : 972-7-467475 
> 84965 Israel                   |
> =========================================================================
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