[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: PC System BIOS and Base Address Register
- To: Mailing List Recipients <pci-sig-request@znyx.com>
- Subject: Re: PC System BIOS and Base Address Register
- From: "David O'Shea" <daveo@corollary.com>
- Date: Wed, 7 Aug 1996 10:15:01 -0700
- Resent-Date: Wed, 7 Aug 1996 10:15:01 -0700
- Resent-From: pci-sig-request@znyx.com
- Resent-Message-Id: <"WAqa11.0.KW2.2_C2o"@dart>
- Resent-Sender: pci-sig-request@znyx.com
Daniele is really right. In addition, I am curious why there is an
advantage to using 10, 18, 20 rather than 10, 14, 18. It would seem
to me that 10,18,20 only has an advantage if you are only partially
decoding the BAR selects. Partial decoding would SURELY NOT be
accetable. If you did this, a BIOS would look at 14 and see the same
thing as 10, which is not OK. (Nevermind, I just realized you were
trying to stay away from the BYTE enables.....). Still Danele is
correct. Even though the BIOS are spec'ed to work with non-compliant
devices, you should not count on this. As I said before, some BIOS
will not handle the 10, 18, 20h case anyway, so unless you don't want
to work in those systems, do it by the book.
At 04:01 PM 8/7/96 +0200, Daniele Beccari wrote:
>A spec is a spec and the PCI spec says (as reported also by Bob
>Goudreau):
>
> "The first Base Address register is always located at offset
> 10h. The second register may be at offset 14h or 18h
> depending on the size of the first. The offsets of
> subsequent Base Address registers are determined by the
> size of previous Base Address registers."
>
>So, w_wong@emulex.com's implementation, whether acceptable, is
>unfortunately not respecting the PCI spec (since he is not using
>64 bits addressing, he must use 14h for his second BAR). Unless
>somebody can prove that "may be" is to be interpreted as
>"if you want it can be"...
û € m