Re: PC System BIOS and Base Address Register

[Bruce Young <Bruce_Young@ccm.jf.intel.com>]

---------------------------- Forwarded with Changes ---------------------------
From: pci-sig-request@znyx.com at SMTPGATE
Date: 8/7/96 4:01PM
*To: pci-sig-request@znyx.com at SMTPGATE
Subject: Re: PC System BIOS and Base Address Register
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A agree with Don James that it is legal to implement non-contiguous Base address
Registers (BARs). I would maintain that a BAR implemented as read-only all zeros
is a request for 0 MB of non-prefetchable 32 bit addressable memory space! 
(check the details in section 6.2.5.1 of the spec) 

So a "Compliant" device can implement a BAR at 10h that requests 1 MB of 32 bit 
addressable space, and another BAR at 20h requesting 16 bytes of I/O space and 
still be fully compliant with the spec. The section of the spec referred to by 
Bob Goudreau was not meant to indicate that no BARs could be skipped. It was 
meant to describe how you parse the BAR section with a mix of 32 bit and 64 bit 
registers. I would agree that unless there are good reasons to do otherwise, it 
is good design practice to put all the "necessary" BARs at the beginning with no
gaps but I do not believe that it is required by the specification.

-Bruce Young
Intel Corporation
On the net I speak for myself, not Intel

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Don James wrote:
     
>Your base address registers do not have to be contiguous. Any BIOS that 
>stops searching when it finds a BAR of 0 will not pass the PCI SIG's 
>compliance tests (specifically the PCIPOST test).
     
and David O'Shea wrote:
     
>System BIOS are supposed to scan all of the Base Address Registers, 
>even if earlier registers were all 0's.   The operating systems which 
>scan the BAR's also adhere to the requirement.   So your implimentation 
>is accetable.
     
in answer to w_wong@emulex.com:
     
> PCI Base Address Registers has total of 6 double words. Can 
> system BIOS skip unused one and allocate resources to
> non-sequential Base Address Registers? In other word, I used 
> only Offset 10h, 18h and 20h Base Address Registers and Skip
> 14h and 1Ch Base Address Registers which are filled with zeros.
     
     
I understand this is just a detail, and it is a good thing that 
BIOSes scan all BARs. However, we should talk about DEVICE compliance 
and not BIOS compliance.
     
A spec is a spec and the PCI spec says (as reported also by Bob 
Goudreau):
     
     "The first Base Address register is always located at offset 
     10h.  The second register may be at offset 14h or 18h 
     depending on the size of the first.  The offsets of 
     subsequent Base Address registers are determined by the
     size of previous Base Address registers."
     
So, w_wong@emulex.com's implementation, whether acceptable, is 
unfortunately not respecting the PCI spec (since he is not using 
64 bits addressing, he must use 14h for his second BAR). Unless 
somebody can prove that "may be" is to be interpreted as
"if you want it can be"...
     
What is the impact of this divergence from the spec? None, thanks
to those who wrote the BIOS compliance tests. But maybe future revisions 
of the spec should have one more line to clear up this issue more 
precisely.
     
Thanks for your attention,
     
     
                    Daniele
     
     
     
     
     
__________________________________________________________ 
Daniele Beccari            Daniele_Beccari@grenoble.hp.com 
Hewlett-Packard, Enterprise Networking & Security Division
ü¸"¨"