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Re: Re[3]: i960RP - host downloading code

:: The RP has a special powerup mode that keeps JUST THE
:: CORE in reset.  This allows a host to download the code 
:: to the RP memory, then release the CORE from reset by
:: clearing a bit in the Extended Bridge Configuration 
:: Register.  This ensures the memory is Pre-loaded before 
:: the RP starts to fetch the IBR.
>  I understand this powerup mode (mode 0 in page 11-5). The proccess
>  seems to be quite clear. The point I don't understrand is this:
>  If the memory is configured to 8 bit (this comes from the fact that 
>  the PMCON is set to 8 bit width on power up, and can't be changed
>  as long as the CORE is held in reset), how can the host transfer 
>  the code data to the 32 bit width memory ?
>                       ------------

Ooohhhh, I get it. Hm..

I see two possible answers: (1) the portion of the memory that
contains the IBI must be 8 bits wide, or (2) the memory device must
have a little extra logic to understand the WIDTH1:0 signals. (Page 13-6.)
Only memory bank 0 (CE#0) is needed for the IBI, and I guess you are
right, it *will* be accesses 8bit at boot.

>  Let me see if I understand. You are actualy saying that if my device 
>  driver cannot control the configuration software, I can't change the
>  window size to more than 4k ? 
>  If this is the case, then the i960RP will give very poor performance...

My intention when I get there is to write a bootstrapper that can be
loaded with the default setup and the CPU held reset. The core can
then be released and real software loaded by the most efficient means

I'm also planning on running the real program out of DRAM. The bootstrap
will load code from the {PCI,ROM,PROM,FLASH} memory and write it into RAM,
and go from there. This will allow me to dispense with icky 8bit memory
stuff quickly.

Steve Williams

"The woods are lovely, dark and deep.  But I have promises to keep,
And lines to code before I sleep, And lines to code before I sleep."