Latency for Bridges

["Belvin Stephen E" <belvin_stephen_e@smtp2.space.honeywell.com>]

Hi:
  I am designing an expansion bus bridge between a backplane bus and PCI.  I
noticed in Revision 2.1 that host bridges are given special consideration for
initial latency (sect. 3.5.3.1, 32 rather than 16 clock cycles).

    Is it the intent of the spec to allow *all* bus-to-bus bridge
    (Base Class 06) devices a maximum initial latency of 32 clocks?

I have spoken to several PCI designers and have received mixed interpretations.
 After all, in some applications the host's access to the PCI bus is through an
expansion bridge.

It seems nearly impossible to design a bus bridge device which doesn't force an
initiator to retry every operation that passes through the bridge.  Without
delayed transactions, operation through a bridge would be impossible.  Even
with the increased complexity and gates, latency is still significant due to
retries.

In my system, the additional 16 clock cycles means having to retry less than
half rather of the transactions rather than *all* operations.

Steve Belvin



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