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state machine 2.0:some thoughts
- To: Mailing List Recipients <pci-sig-request@znyx.com>
- Subject: state machine 2.0:some thoughts
- From: tw38966@is1.bfu.vub.ac.be (Rafiki Kim Hofmans)
- Date: Sat, 10 Aug 1996 23:48:46 +0200 (DST)
- Resent-Date: Sat, 10 Aug 1996 23:48:46 +0200 (DST)
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On page 131 of the book "PCI system architecture" :
"the initiator doesn't have to assert IRDY immedately upon entering a data
phase"
Does this also count for a single data phase ?
Because the book also says:
"The initiator asserts IRDY# to indicate that it is ready to
receive the first data item from the target ... if this were the final
data phase, the initiator would assert IRDY# and deassert FRAME#.."
According to the state machine on page 175 of the specs 2.0,
it looks like IRDY# has to be asserted immediately upon entering a SINGLE
data phase
-> state = b_busy
goto b_busy if (not FRAME# OR not IRDY#) AND not(hit)
goto s_data if (not FRAME# OR not IRDY#) AND hit....
So, can I assume that for a single data phase, IRDY# must be asserted
IMMEDIATELY upon entering the data phase ??
Thanks in advance !
Kim
ì Û