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Re[5]: i960RP - host downloading code
- To: Mailing List Recipients <pci-sig-request@znyx.com>
- Subject: Re[5]: i960RP - host downloading code
- From: Noam Efrati <noam@genie.terra.co.il>
- Date: Sun, 11 Aug 1996 10:56:32 +0300 (IDT)
- Cc: pci-sig@znyx.com
- In-Reply-To: <Fri, 09 Aug 96 07:46:01 PDT_2@ccm.jf.intel.com>
- Resent-Date: Sun, 11 Aug 1996 10:56:32 +0300 (IDT)
- Resent-From: pci-sig-request@znyx.com
- Resent-Message-Id: <"rXvgB2.0.6Q1.uAP3o"@dart>
- Resent-Sender: pci-sig-request@znyx.com
Text item:
The last mail (Re[4]) was very clear and helpfull.
I still have one last question (for now):
Synce the translate value register is a read only through
configuration space, then if the inbound ATU window is pointing
to the SRAM on local bus (say address fd000000, then the host cannot
move this pointer without an intervention of the core processor.
This means that a complex mechanism has to be used, in which
the host passes the desired value of the tralnslte register
to the i960 by using the MU or something like that.
Am I right ?
Thanks in advance,
=========================================================================
Noam Efrati | e-mail: noam@terra.co.il
Terra computers ltd. | phone : 972-7-467502
6 Ashuach st., Omer, | fax : 972-7-467475
84965 Israel |
=========================================================================
Πz