state machine 2.0:some thoughts

[tw38966@is1.bfu.vub.ac.be (Rafiki Kim Hofmans)]

> 
> >On page 131 of the book "PCI system architecture" :
> >
> >"the initiator doesn't have to assert IRDY immedately upon entering a >data
> >phase"
> >
> >Does this also count for a single data phase ?
> >Because the book also says:
> >
> >        "The initiator asserts IRDY# to indicate that it is ready to
> >receive the first data item from the target ... if this were the final
> >data phase, the initiator would assert IRDY# and deassert FRAME#.."
> 
> The problem is that a "DATA PHASE" is actually a clock cycle which
> is not an "ADDRESS/COMMAND PHASE". So, you can have a data phase
> WITHOUT DATA TRANSFER. Your first excerpt from the spec says that
> after the address phase, if the initiator is not ready it doesn't
> have to assert IRDY immediately. But the clock cycle is still called
> a DATA PHASE. If your initiator is ready, it can assert IRDY
> immediately and wait for TRDY. Once again, if the target is not
> ready it will not assert TRDY, but the cycle will still be called a
> DATA PHASE (without data transfer).
> 

Maybe I didnt make myself clear what I was trying to ask, sorry for that.
I'll formulate it this way :

IF I have a SINGLE data transfer :

PCI specs2.0 on p174 

	STATE=IDLE
	goto B_BUSY if !FRAME#*!HIT

Suppose on clock 2, FRAME is asserted,address is latched, slow decoding ->
goto state B_BUSY

on p175
	next STATE=B_BUSY
	goto B_BUSY if(!FRAME#+!IRDY)*!HIT

For a single data transfer, FRAME must be deasserted at clock 3.
And suppose the address is still not decoded.
So this equation tells that IRDY# must be asserted IMMEDIATELY after the
address phase.
This equation also tells that for a BURST, IRDY# does NOT have to be
asserted immediately after the address phase.	
Because in this case, FRAME is still asserted indicating that this isn't
the last data phase.

Second problem :

p175
	STATE=B_BUSY
	goto B_BUSY if(!FRAME#+!IRDY)*!HIT
	goto IDLE if FRAME#
	goto S_DATA if (!FRAME#+!IRDY)*HIT*...

I'm confused about the second equation.
If the address is decoded with a base address match, but FRAME is
deasserted because we're in a SINGLE data phase.
I should go to S_DATA.
But the second equation tells me also that I should go to IDLE because
FRAME is deasserted. 

So my first question is :
can I assume that IRDY must be asserted immediately after the address
phase for a single data phase ?

Second question :
What's the use of GOTO IDLE in the state B_BUSY ?

Thanks in advance !

Kim

TC