Re[6]: i960RP - host downloading code

[Byron R Gillespie <Byron_R_Gillespie@ccm.ch.intel.com>]

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     See comments below//
     byron


______________________________ Reply Separator _________________________________
Subject: Re[5]: i960RP - host downloading code
Author:  noam@genie.terra.co.il at SMTPGATE
Date:    8/11/96 10:56 AM


  The last mail (Re[4]) was very clear and helpfull.
     
  I still have one last question (for now):
     
     
     
Synce the translate value register is a read only through 
configuration space, then if the inbound ATU window is pointing
to the SRAM on local bus (say address fd000000, then the host cannot 
move this pointer without an intervention of the core processor. 
This means that a complex mechanism has to be used, in which
the host passes the desired value of the tralnslte register 
to the i960 by using the MU or something like that.
     
Am I right ?
//
// yes you are correct.  Once you change the inbound translate
// value register, you cannot access the PMMR's any more.  Therefore
// you must download the code, release the processor from reset
// then do any communications with the 960.
//
// byron
// 
     
     
Thanks in advance,
     
========================================================================= 
Noam Efrati                    | e-mail: noam@terra.co.il
Terra computers ltd.            | phone : 972-7-467502 
6 Ashuach st., Omer,           | fax   : 972-7-467475 
84965 Israel                   |
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Subject: Re[5]: i960RP - host downloading code
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To: Byron R Gillespie <Byron_R_Gillespie@ccm.ch.intel.com>
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Date: Sun, 11 Aug 1996 10:56:32 +0300 (IDT)
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