Re: Transaction abort

["John R Pierce" <pierce@scruznet.com>]

As I understand it, on the retry-disconnects, the CPU stays in a wait state
(assuming its write posting fifo backs up) while the host bridge does
target retries.

I'm not sure what happens on a target abort.  Its fairly complex due to the
write posting fifos present in both most modern CPU's _AND_ most modern
host-PCI bridge chipsets.

-jrp

----------
> From: Rafi Boneh <RAFIB@GILAT.MHS.CompuServe.COM>
> To: Mailing List Recipients <pci-sig-request@znyx.com>
> Subject: Transaction abort
> Date: Wednesday, August 14, 1996 11:04 PM
> 
> Hi.
> 
> Suppose I am trying to burst from a host PC as a master, to a slave PCI
> board, by copying data from the host memory, to the board, by the CPU.
> What happens if my board stops the transaction by doing Retry, Disconnect

> 
> or Target-Abort, or the PCI arbitrator force the host to do a 
> Master-Abort?
> How can the CPU know that the transaction was interrupted, and after how
> many data phases?
> Dose the host bridge generates some kind of exception the CPU  in this 
> case?
> 
> I'd appreciate any comment.
> 
> Rafi Boneh.
> 
> 
5
@/