[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: steering the BE# ?
- To: Mailing List Recipients <pci-sig-request@znyx.com>
- Subject: Re: steering the BE# ?
- From: "John R Pierce" <pierce@scruznet.com>
- Date: Sat, 17 Aug 1996 16:11:47 -0700
- Resent-Date: Sat, 17 Aug 1996 16:11:47 -0700
- Resent-From: pci-sig-request@znyx.com
- Resent-Message-Id: <"K1hAl1.0.1k4.mCb5o"@dart>
- Resent-Sender: pci-sig-request@znyx.com
> From: Rafiki Kim Hofmans <tw38966@is1.bfu.vub.ac.be>
> To: Mailing List Recipients <pci-sig-request@znyx.com>
> Subject: steering the BE# ?
> Date: Saturday, August 17, 1996 3:51 PM
>
> Hi,
>
> how can I steer the BE# ?
>
> e.g for a target-only device :
>
> Suppose I want to do a write a byte to targetaddress (Base address +
> 0001) with IO mapped IO.
> How can I set the BE#, can it be done through software ?
Just do a _outp(Base+1, data); or mov dx,base+1 ; out dx,al
> Suppose I want to write a double word to targetaddress (Base address +
> 0011) with IO mapped IO, what happens with the BE# ?
Um, dword writes must be to dword aligned boundarys. If you were to do a
<out dx,eax> to a odd address like base+0x0011, the CPU would probably do a
byte write to 0011, a word write to 0012, and a byte write to 0014... [i
don't -think- a intel processor bridge would do a 3 byte write to 0011
> And in case of a memory mapped IO write to the same address, what happens
> with AD1 and AD0 ?
Same as any other memory cycle... No difference between memory mapped IO
and memory mapped memory except the IO is more likely to be tagged
non-prefetchable and non-cacheable.
-jrp
G ô â