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Re: steering the BE# ?
- To: Mailing List Recipients <pci-sig-request@znyx.com>
- Subject: Re: steering the BE# ?
- From: "Monish Shah" <monish@mcsy2.fc.hp.com>
- Date: Mon, 19 Aug 1996 09:59:27 -0600
- In-Reply-To: "John R Pierce" <pierce@scruznet.com> "Re: steering the BE# ?" (Aug 17, 4:11pm)
- References: <199608172315.QAA26521@scruz.net>
- Resent-Date: Mon, 19 Aug 1996 09:59:27 -0600
- Resent-From: pci-sig-request@znyx.com
- Resent-Message-Id: <"NctYz1.0.dA.uU96o"@dart>
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On Aug 17, 4:11pm, John R Pierce wrote:
> Subject: Re: steering the BE# ?
> > From: Rafiki Kim Hofmans <tw38966@is1.bfu.vub.ac.be>
> > To: Mailing List Recipients <pci-sig-request@znyx.com>
> > Subject: steering the BE# ?
> > Date: Saturday, August 17, 1996 3:51 PM
> >
> > Hi,
> >
> > how can I steer the BE# ?
> >
> > e.g for a target-only device :
> >
> > Suppose I want to do a write a byte to targetaddress (Base address +
> > 0001) with IO mapped IO.
> > How can I set the BE#, can it be done through software ?
>
> Just do a _outp(Base+1, data); or mov dx,base+1 ; out dx,al
Just for clarification, let me note that in this case AD[1:0] will be 01
and only BE[1] will be asserted.
> > Suppose I want to write a double word to targetaddress (Base address +
> > 0011) with IO mapped IO, what happens with the BE# ?
>
> Um, dword writes must be to dword aligned boundarys. If you were to do a
> <out dx,eax> to a odd address like base+0x0011, the CPU would probably do a
> byte write to 0011, a word write to 0012, and a byte write to 0014... [i
> don't -think- a intel processor bridge would do a 3 byte write to 0011
I can't speak for all implementations, but I know that there are at least
some implementations where the result would be a byte write to 0x0011
followed by a 3 byte write to 0x0012.
> > And in case of a memory mapped IO write to the same address, what happens
> > with AD1 and AD0 ?
>
> Same as any other memory cycle... No difference between memory mapped IO
> and memory mapped memory except the IO is more likely to be tagged
> non-prefetchable and non-cacheable.
I think the question was, how does memory mapped I/O differ from I/O mapped
I/O, as far as AD1 and AD0 are concerned? The answer is: AD1 and AD0
encode the burst order in a memory mapped I/O write on PCI - they do not
contain "address" information. So, a byte write to 0x0001 will likely
leave AD1 and AD0 at 00 while still asserting BE[1].
See page 28 of PCI spec 2.1 for more information on the burst order.
> -jrp
Monish Shah
Hewlett Packard
P $