PCI I/O Space Consumption Limitation

["Belvin Stephen E" <belvin_stephen_e@smtp2.space.honeywell.com>]

Hi.
  I am developing a PCI expansion bus bridge and am concerned about what
appears to be an I/O space consumption limitation.
  Page 197 of the PCI Rev 2.1 spec states "Devices that map control functions
into I/O space may not consume more than 256 bytes per I/O Base Address
Register."  In response to this and repeated recommendations to minimize I/O
space, I find that many devices are encouraged to minimize I/O space.  In one
book I read that "... subsystem designers should design a function so as to
require no more than 32 bytes of user-definable configuration data."
  I am well aware of the shrinking Intel I/O space problem but not all systems
have I/O space limitations.  My system will use a MIPS processor and we plan to
implement a large I/O space (from 10KB to 1MB).  Where practical, we follow
IEEE Std 1212 register definitions as a guide, where I/O space is sacrificed
for well organized control and status registers.  Fire Wire also follows this
in its register organization.
  I would think PowerPC host bridges would not find 10-20KB of I/O space to be
a problem.
  My question is:

  o   Do designers follow the statement on page 197 and implement
      multiple I/O BARs where more than 256 bytes of I/O space
      are consumed?

  TIA.
Steve Belvin
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