FW: PCI I/O Space Consumption Limitation

["Belvin Stephen E" <belvin_stephen_e@smtp2.space.honeywell.com>]

Monish Shah:

> On Aug 21,  4:59pm, Belvin Stephen E wrote:
  > > Subject: PCI I/O Space Consumption Limitation
  > > Hi.
  > >   I am developing a PCI expansion bus bridge and am
  > > concerned about what appears to be an I/O space
  > > consumption limitation.
  > >   Page 197 of the PCI Rev 2.1 spec states "Devices
  > > that map control functions into I/O space may not
  > > consume more than 256 bytes per I/O Base Address
  > > Register."  In response to this and repeated
  > > recommendations to minimize I/O space, I find that
  > > many devices are encouraged to minimize I/O space.
  > > In one book I read that "... subsystem designers
  > > should design a function so as to require no more
  > > than 32 bytes of user-definable configuration data."
  > >   I am well aware of the shrinking Intel I/O space
  > > problem but not all systems have I/O space
  > > limitations.  My system will use a MIPS processor
  > > and we plan to implement a large I/O space (from
  > > 10KB to 1MB).  Where practical, we follow IEEE
  > > Std 1212 register definitions as a guide,
  > > where I/O space is sacrificed for well organized
  > > control and status registers.  Fire Wire also
  > > follows this in its register organization.
  > >  I would think PowerPC host bridges would not
  > > find 10-20KB of I/O space to be a problem.

> I hope you are not confused by the terms I/O space and memory
> space.  PCI memory space is actually memory mapped I/O space.
> On RISC processors, that's all you have.  Dealing with the
> PCI I/O space only creates hassles for these systems.
> I'm sure when you are talking about being able to get lots
> of I/O space in MIPS and PowerPC systems, it applies to
> memory mapped I/O space.  To use that, ask for memory space,
> not I/O space.

> Your confusion (if, indeed, you are confused) probably stems
> from the fact that RISC processors call their memory mapped
> I/O space simply I/O space, since they don't have the x86
> style I/O space.

Yes, indeed, any I/O space is actually memory mapped in these systems.  Since
we are dealing with I/O registers, I simply called it I/O space.  According to
PCI, it is I/O space if the lsb of a BAR says so.

> Let me also note, unless you have some legacy drivers
> that need to work with your PCI card or you have some
> BIOS issues forcing you to put stuff in I/O space,
> you should just put everything in memory space.  That
> works fine in PCs and works well everywhere else too.

Based on this and some other Intel PC specific discussions, I have been
converted.  In fact, I now dislike the definition of any I/O BARs.

  > >   My question is:
  > >
  > >   o   Do designers follow the statement on page 197 and implement
  > >       multiple I/O BARs where more than 256 bytes of I/O space
  > >       are consumed?

> If not, they wouldn't have much hope of working in a PC that has ISA.

PCI designers should be aware of these limitations even if their target
system(s) is not Intel PCs.  You never know when a design might enter the
largest PCI system market!

  > >   TIA.
  > > Steve Belvin

> Monish Shah
> Hewlett Packard

I appreciate this and other discussions on address decoding that you have
participated in.

Steve
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From: "Monish Shah" <monish@mcsy2.fc.hp.com>
Message-Id: <9608211655.ZM13111@hpfcmss.fc.hp.com>
Date: Wed, 21 Aug 1996 16:55:06 -0600
In-Reply-To: "Belvin Stephen E" <belvin_stephen_e@smtp2.space.honeywell.com>
        "PCI I/O Space Consumption Limitation" (Aug 21,  4:59pm)
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