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Re: Re[2]: PCI I/O Space Consumption Limitation
- To: Mailing List Recipients <pci-sig-request@znyx.com>
- Subject: Re: Re[2]: PCI I/O Space Consumption Limitation
- From: "John R Pierce" <pierce@scruznet.com>
- Date: Thu, 22 Aug 1996 02:34:47 -0700
- Resent-Date: Thu, 22 Aug 1996 02:34:47 -0700
- Resent-From: pci-sig-request@znyx.com
- Resent-Message-Id: <"O0rU81.0.I87.c137o"@dart>
- Resent-Sender: pci-sig-request@znyx.com
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> From: Taylor, Mike <mike@buntypost.dundee.ncr.com>
> To: Mailing List Recipients <pci-sig-request@znyx.com>
> Subject: FW: Re[2]: PCI I/O Space Consumption Limitation
> Date: Thursday, August 22, 1996 2:00 AM
>
> I thought PCI/ISA bridges used subtractive decode and therefore were only
> active in address spaces not acknowledged by any PCI bus. Aliasing by an
> ISA card would therefore be prevented in any PCI used I/O space. The 256
> bytes per I/O BAR restriction is therefore not due to ISA limitations.
>
Say we had a ISA I/O device like the old Media Vision Pro Audio Spectrum 16...
This used 10 bit decode 0x388 and virtually ALL aliases (0xB88,0x1388, etc etc
etc) for additional registers. If a PCI card used ANY 4K I/O space, it would
prempt some set of these ports from operation. This is just a example, and an
extreme one at that, but that was the rational behind restricting PCI I/O
decodes to using addresses that had a bbbb.bb00.xxxx.xxxx binary address.
Basically, any modern PCI device should be memory mapped in PC terminology. To
a RISC engine, its all the same thing. PC I/O space exists only for legacy
purposes.
-jrp
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