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Delayed (initial) IRDY
- To: Mailing List Recipients <pci-sig-request@znyx.com>
- Subject: Delayed (initial) IRDY
- From: robert@lsi.melco.co.jp (streitenberger robert)
- Date: Thu, 22 Aug 96 21:57:16 JST
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I have a question about the initial assertion of IRDY by the initiating master
The following scenario is (apparently) legal:
_| | | | |_______|
FRAME |_______|_______|_______|_______| |-------
| | | | | |
|_______|_______|_______|_______|_______|
AD X_______X_______X_______X_______X_______X-------
| | | | | |
IRDY _|_______|_______|_______|_______| |_______
| | | | |_______|
| | | | | |
_|_______|_______| | | |_______
TRDY | | |_______|_______|_______|
| | | | | |
_|_______|_______| | | |_______
DEVSEL | | |_______|_______|_______|
| | | | | |
_|_______|_______| | | |_______
STOP | | |_______|_______|_______|
| | | | | |
I would expect IRDY to go low one cycle after FRAME goes low.
However, some Chip Sets seem to delay the initial assertion of IRDY.
Currently my chip would fail i.e. I would deassert TRDY/DEVSEL/STOP
not together with IRDY but one cycle later:
_| | | | |_______|
FRAME |_______|_______|_______|_______| |-------
| | | | | |
|_______|_______|_______|_______|_______|
AD X_______X_______X_______X_______X_______X-------
| | | | | |
IRDY _|_______|_______|_______|_______| |_______
| | | | |_______|
| | | | | |
_|_______|_______| | | |
TRDY | | |_______|_______|_______|_______|
| | | | | |
_|_______|_______| | | |
DEVSEL | | |_______|_______|_______|_______|
| | | | | |
_|_______|_______| | | |
STOP | | |_______|_______|_______|_______|
This is a violation of the spec.
I have three questions:
(1) How common is the above scenario i.e. how many chip sets
would delay the initial assertion of IRDY ?
(2) Am I the only one that would get 'confused' in case of the above scenario ?
(3) What would happen if I responded the latter way (in the real 'world')
Thanks in advance !!!
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ROBERT STREITENBERGER (Engineer) Phone: +81 727 84 7345
/\ Image Processing VLSI Design /\ FAX: +81 727 84 7439
_\/_ LSI Development Department B _\/_ E-mail: robert@lsi.melco.co.jp
/_/\_\ System LSI Laboratory /_/\_\
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