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asymmetrical target and master interfaces
- To: Mailing List Recipients <pci-sig-request@znyx.com>
- Subject: asymmetrical target and master interfaces
- From: v_chau@emulex.com (Vi Chau)
- Date: Thu, 22 Aug 96 11:41:02 PDT
- Resent-Date: Thu, 22 Aug 96 11:41:02 PDT
- Resent-From: pci-sig-request@znyx.com
- Resent-Message-Id: <"nXtBJ3.0.TY1.CeA7o"@dart>
- Resent-Sender: pci-sig-request@znyx.com
Hi, Everyone,
I have a question regarding the setup and operation of PCI devices that have
asymmetrical target and master interfaces.
We are currently developing an ASIC for a PCI interface. The PCI logic includes
a target interface that supports dual-address cycles (>32-bit address) and a
master interface that only supports 32-bit address.
What I heard from our driver writers is that this present a problem for them
because systems and OS's tend to be confused when they see our BAR's supporting
64-bit addresses and assume that all addresses used by this device would be
64-bit. This causes a lot of headache for the drivers.
Does anyone has any experience with such a device? Do you have the same sort
of problems?
Given that operating systems such as Windows NT are only 32-bit, how does it
react to a PCI device that tells the OS that it can be mapped anywhere within
the 64-bit address range?
Thanks in advance for your ideas and answers.
Vi chau
Emulex Corp.
3535 Harbor Blvd.
Costa Mesa, CA 92626
(714) 513-8132
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